Not just thermal reasons! For instance, keeping caches coherent across so many cores is a great challenge. That's what Intel was experimenting with on Knights C

Not just thermal reasons! For instance, keeping caches coherent across so many cores is a great challenge. That's what Intel was experimenting with on Knights Corner - and many think they screwed it up quite a bit - with the ring bus + L2 implementation. However, they did learn a lot and a very similar ring bus based cache coherence implementation works quite well on Xeons for up to 18C - although it's worth noting that for >8C there are actually two rings -, and it should work pretty well on "regular" Xeons for at least a couple of more generations. However, not unexpectedly, KNL is switching to a 2D mesh (see http://goo.gl/SE8pZV http://goo.gl/SE8pZV).