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GPUs are in an interesting place. They were not able to scale under 28nm due to the increased static leakage. Intel CPUs were able to scale because of dynamic p
by yvdriess 11y ago
GPUs are in an interesting place. They were not able to scale under 28nm due to the increased static leakage. Intel CPUs were able to scale because of dynamic power management, but GPUs cannot really use the same trick. It's only with the upcoming 16nm GPU generation that they got static leakage to a place where we see an actual new generation of GPU hardware. It's been about 5 years now of 28nm + GDDR4.
- thesz 11y agoThe lengths you mentioned are lambdas - factors for on-die features. This means that some part of the transistor cannot be smaller than lambda-size square. Usually, they are much bigger and often are of equal size even for wastly different lambdas. Here's a table for SPARC CPUs, with process lambda, die size and transistor count: https://en.wikipedia.org/wiki/SPARC#SPARC_microprocessor_implementations https://en.wikipedia.org/wiki/SPARC#SPARC_microprocessor_imp... If transistors would reduce with lambda, then for two-fold reduction you would get four fold increase of density. Difference in density between T4 and T2 (90 and 40 hn processes) is less than two. The static leakage you mentioned is mainly due to sizes of transistor parts. You should also know that NVidia uses humans as chip designers (they can afford that), not an automatic process like some fabless companies use. And now I get to my main point: NVidia overshot with 28nm and got transistors features that were too small, probably, due to not all that good software they used to calculate models. They continue to overshoot for 5 years until they corrected their overshoot. It has nothing to do with process lambda. It is process error in NVidia.