4 ms·

Fortunately for servers things are still cranking along with Moore's Law for now, going into increasing core counts which have roughly doubled every two years s

Fortunately for servers things are still cranking along with Moore's Law for now, going into increasing core counts which have roughly doubled every two years since Nehalem, with the result that now we have 18 core Haswell EP parts, with 22 cores to come with Broadwell and 28(?) cores with Skylake. Of course after that things are likely to start flattening with the slower transition to 10nm. It is interesting that the cache per core has not really increased over this time, being fixed at ~2.5MB of L3 per core. Naively one might have expected some of the additional transistor budget to be given over to increased cache per core, but clearly Intel has found this number to be the sweet spot.

userbinator 11y ago
Caches can't get too big, or they'll start becoming slower, which defeats the purpose of having a cache.
- wtallis 11y ago
  Thus, Intel's solution for improving their integrated graphics performance was to introduce an L4 cache implemented as off-die on-package eDRAM, rather than try to make the L3 cache big enough.
cm2187 11y ago
True. That being said I don't think the computing power increases linearly with the number of cores. I presume for thermal reasons, the more cores you have in a Xeon, the lower the frequency at which they can simultaneously operate. So as it stands doubling the number of cores doesn't mean doubling the computing power.
- slizard 11y ago
  Not just thermal reasons! For instance, keeping caches coherent across so many cores is a great challenge. That's what Intel was experimenting with on Knights Corner - and many think they screwed it up quite a bit - with the ring bus + L2 implementation. However, they did learn a lot and a very similar ring bus based cache coherence implementation works quite well on Xeons for up to 18C - although it's worth noting that for >8C there are actually two rings -, and it should work pretty well on "regular" Xeons for at least a couple of more generations. However, not unexpectedly, KNL is switching to a 2D mesh (see http://goo.gl/SE8pZV http://goo.gl/SE8pZV).

userbinator 11y ago

Caches can't get too big, or they'll start becoming slower, which defeats the purpose of having a cache.

wtallis 11y ago
Thus, Intel's solution for improving their integrated graphics performance was to introduce an L4 cache implemented as off-die on-package eDRAM, rather than try to make the L3 cache big enough.

cm2187 11y ago

True. That being said I don't think the computing power increases linearly with the number of cores. I presume for thermal reasons, the more cores you have in a Xeon, the lower the frequency at which they can simultaneously operate. So as it stands doubling the number of cores doesn't mean doubling the computing power.

slizard 11y ago
Not just thermal reasons! For instance, keeping caches coherent across so many cores is a great challenge. That's what Intel was experimenting with on Knights Corner - and many think they screwed it up quite a bit - with the ring bus + L2 implementation. However, they did learn a lot and a very similar ring bus based cache coherence implementation works quite well on Xeons for up to 18C - although it's worth noting that for >8C there are actually two rings -, and it should work pretty well on "regular" Xeons for at least a couple of more generations. However, not unexpectedly, KNL is switching to a 2D mesh (see http://goo.gl/SE8pZV http://goo.gl/SE8pZV).