To build on what you said: we're interested in the cache line, not the data in that cache line. Both reads and stores access the cache line, and both can see mi

To build on what you said: we're interested in the cache line, not the data in that cache line. Both reads and stores access the cache line, and both can see misses. It's not that you're seeing cached data, it's that your store instruction does not have to wait for the cache line to come into the L1.