Yes, as the designers of the RISC-V ISA (an unrelated recently-designed ISA) explain (http://riscv.org/spec/riscv-spec-v2.0.pdf http://riscv.org/spec/riscv-spec

Yes, as the designers of the RISC-V ISA (an unrelated recently-designed ISA) explain (http://riscv.org/spec/riscv-spec-v2.0.pdf http://riscv.org/spec/riscv-spec-v2.0.pdf page 17): "Both conditional move and predicated instructions add complexity to out-of-order microarchitectures, adding an implicit third source operand due to the need to copy the original value of the destination architectural register into the renamed destination physical register if the predicate is false." But removing predicated instructions on 64-bit ARM freed four bits on the encoding of every instruction. What's the obvious use for four extra instruction bits? Adding one bit to each register field, thus doubling the number of registers. That is, my guess is that having twice the number of ISA-visible registers was a consequence of removing the predication bits, not its cause.