3 ms·
I would doubt an ASIC would be worth it, giving the number of organisations needing this CODEC would be relatively low. An ASIC run is expensive and even more e
by doc_holliday 11y ago
I would doubt an ASIC would be worth it, giving the number of organisations needing this CODEC would be relatively low. An ASIC run is expensive and even more expensive if there is subsequent error in the design.
FPGA makes sense for this application. It can always be re-flashed.
- jhallenworld 11y agoThey should at least enable the SEU mitigation circuit, which repeatedly performs CRC of the configuration data. Have it reboot if it detects an error. Maybe they already do this. I checked, Zynq-7000 has this capability: http://www.xilinx.com/products/intellectual-property/sem.html http://www.xilinx.com/products/intellectual-property/sem.htm...