There is something in between nothing and a full IOMMU. I've been working with a TMS570 processor lately whose DMA engine supports an IOMPU. This hardware is

There is something in between nothing and a full IOMMU. I've been working with a TMS570 processor lately whose DMA engine supports an IOMPU. This hardware is equivalent to the Cortex-R/M Memory protection unit. An MPU has all of the same protection domains that an MMU does, except for a few major differences: - The total number of protected regions is very small (12 or so), such that the hardware cost is somewhat smaller than a TLB cache. - To offset the small number of regions, the size of each region can be almost any power of two. - The MPU does not perform address translation, again reducing the hardware cost. Thus, the kernel can configure the peripheral's DMA engine to only allow access to a page or few.