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Whenever I've glanced through the errata for processors, it makes me think it's a miracle that the CPUs run as well as they do... https://www-ssl.intel.com/con

Whenever I've glanced through the errata for processors, it makes me think it's a miracle that the CPUs run as well as they do... https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf#21 https://www-ssl.intel.com/content/dam/www/public/us/en/docum...

ciupicri 11y ago
I guess that's why Xeon is a bit behind, so that they can fix those bugs.
- ksec 11y ago
  My thoughts as well, I guess that is Why things are taking a lot longer for Xeon E5.
  - rincebrain 11y ago
    Xeon E5 and E7 are always longer because getting SMP working reliably can reveal all sorts of bugs that never arise when you have One True Processor Die.
    - deelowe 11y ago
      And more PCIE lanes, more cores, more cache, etc...
nickpsecurity 11y ago
Take a look at the challenges at 28nm: http://electronicdesign.com/digital-ics/understanding-28-nm-soc-design-arm-based-cores http://electronicdesign.com/digital-ics/understanding-28-nm-... You're right that it's damn-near a miracle that they work. The miracle is the investment of literally billions in tooling and projects to figure out how to get it to work. Then, it's still so expensive that cutting-edge nodes at 28nm and below where Intel often works are exclusive to only the elite engineers and tools if it's anything of significant size.
- _yosefk 11y ago
  I dunno, Adapteva taped out at 28nm with 5 people. Do you mean that full custom design is particularly hard at 28nm or that it's hard for EDA vendors? 28nm is also a bulk node, I think it ought to have been easier to understand for everyone relatively to FinFET nodes.
  - nickpsecurity 11y ago
    I've given them props before as they're a special case. They wrote a whole blog article on how they kept things cheap. In comments in past 48 hours, they mentioned something like $2-3 million in 3 years to get their relatively simple design done. I also remember they deal with HPC crowd that pays good money for even low-volume. So, they're just unusual across the board. Doesn't tell us much about a large design except to say physics will fight us every step of the way. Various approaches like asynchronous and self-correcting circuits might help us a bit. Look at Achronix FPGA's to see the power of the former.
  - gluggymug 11y ago
    Uh, tape out doesn't mean you've verified anything properly. Looking at the various Intel bugs found, I can't help sniggering a little. Verification mistakes happen all the time though. It's just a matter of when the bugs are found: if found later, it has much greater impact. On the 28nm issue, getting your design to synthesize to 28 nm depends on the architecture and your constraints. Trickier data paths make it harder to get it meeting timing. Where your IOs are placed, where your RAMs are placed and how much you have, each thing can make it harder and harder to synthesize. Adapteva doesn't have much RAM I believe.
    - _yosefk 11y ago
      Well, yeah, I'm just saying it wasn't a picnic at 40nm or 90nm, either. It didn't go from a walk in the park to a nightmare at 28nm. Also I believe all the bugs in TFA are logical bugs where the circuit would have misbehaved in a logical simulation, not the kind where the circuit "flips zeros to ones" or vice versa because of physical implementation issues. In this sense advanced nodes make things worse only indirectly by enabling larger, more complex designs.
velox_io 11y ago
It's also amazing that with over 5 billion transistors (on a high E5). It's not transistors the cause the errors but the CPU design.

ciupicri 11y ago

I guess that's why Xeon is a bit behind, so that they can fix those bugs.

ksec 11y ago
My thoughts as well, I guess that is Why things are taking a lot longer for Xeon E5.
- rincebrain 11y ago
  Xeon E5 and E7 are always longer because getting SMP working reliably can reveal all sorts of bugs that never arise when you have One True Processor Die.
  - deelowe 11y ago
    And more PCIE lanes, more cores, more cache, etc...

nickpsecurity 11y ago

Take a look at the challenges at 28nm: http://electronicdesign.com/digital-ics/understanding-28-nm-soc-design-arm-based-cores http://electronicdesign.com/digital-ics/understanding-28-nm-... You're right that it's damn-near a miracle that they work. The miracle is the investment of literally billions in tooling and projects to figure out how to get it to work. Then, it's still so expensive that cutting-edge nodes at 28nm and below where Intel often works are exclusive to only the elite engineers and tools if it's anything of significant size.

_yosefk 11y ago
I dunno, Adapteva taped out at 28nm with 5 people. Do you mean that full custom design is particularly hard at 28nm or that it's hard for EDA vendors? 28nm is also a bulk node, I think it ought to have been easier to understand for everyone relatively to FinFET nodes.
- nickpsecurity 11y ago
  I've given them props before as they're a special case. They wrote a whole blog article on how they kept things cheap. In comments in past 48 hours, they mentioned something like $2-3 million in 3 years to get their relatively simple design done. I also remember they deal with HPC crowd that pays good money for even low-volume. So, they're just unusual across the board. Doesn't tell us much about a large design except to say physics will fight us every step of the way. Various approaches like asynchronous and self-correcting circuits might help us a bit. Look at Achronix FPGA's to see the power of the former.
- gluggymug 11y ago
  Uh, tape out doesn't mean you've verified anything properly. Looking at the various Intel bugs found, I can't help sniggering a little. Verification mistakes happen all the time though. It's just a matter of when the bugs are found: if found later, it has much greater impact. On the 28nm issue, getting your design to synthesize to 28 nm depends on the architecture and your constraints. Trickier data paths make it harder to get it meeting timing. Where your IOs are placed, where your RAMs are placed and how much you have, each thing can make it harder and harder to synthesize. Adapteva doesn't have much RAM I believe.
  - _yosefk 11y ago
    Well, yeah, I'm just saying it wasn't a picnic at 40nm or 90nm, either. It didn't go from a walk in the park to a nightmare at 28nm. Also I believe all the bugs in TFA are logical bugs where the circuit would have misbehaved in a logical simulation, not the kind where the circuit "flips zeros to ones" or vice versa because of physical implementation issues. In this sense advanced nodes make things worse only indirectly by enabling larger, more complex designs.

velox_io 11y ago

It's also amazing that with over 5 billion transistors (on a high E5). It's not transistors the cause the errors but the CPU design.