It's a process called scan chain insertion. As a chip designer, I can tell you that DFT (Design for Test, which scan chain falls under) can be a real PITA even

It's a process called scan chain insertion. As a chip designer, I can tell you that DFT (Design for Test, which scan chain falls under) can be a real PITA even though the tools are automated. EDIT: Should have also said that it really isn't that big in terms of area... a register plus two wires is nothing in the scheme of things. https://en.wikipedia.org/wiki/Scan_chain https://en.wikipedia.org/wiki/Scan_chain