4 ms·

I recommend this CCC presentation by an AMD engineer: https://media.ccc.de/v/32c3-7171-when_hardware_must_just_work https://media.ccc.de/v/32c3-7171-when_hardwa

I recommend this CCC presentation by an AMD engineer: https://media.ccc.de/v/32c3-7171-when_hardware_must_just_work https://media.ccc.de/v/32c3-7171-when_hardware_must_just_wor... The bottom line is that as a last resort debugging method, all modern chips can do scan dumps, which means reading out the state of every flip-flop on the chip. Obviously I have no idea whether that was needed by Intel to find this bug. It's possible that a higher-level emulation or some other technique was sufficient. But when all else fails, you can still do scan dumps.

wyager 11y ago
That sounds incredibly expensive to route. Every flip flop?
- trsohmers 11y ago
  It's a process called scan chain insertion. As a chip designer, I can tell you that DFT (Design for Test, which scan chain falls under) can be a real PITA even though the tools are automated. EDIT: Should have also said that it really isn't that big in terms of area... a register plus two wires is nothing in the scheme of things. https://en.wikipedia.org/wiki/Scan_chain https://en.wikipedia.org/wiki/Scan_chain
- nhaehnle 11y ago
  Kind of, but it's a chain. It works by shifting bits through all flip-flops until they've all "dropped out" of an I/O pin. So you don't need any expensive muxes or crossbars. It's actually one of the largest and most realistic real-world application of TSP and related problems.
- PhantomGremlin 11y ago
  That sounds incredibly expensive to route. Every flip flop? Almost all ICs nowadays already have scan chains connecting to 99+% of their internal flip flops. This is because it literally has been decades since chips have gotten too complex to do reasonable "functional" tests on chips in production. These tests are used not to verify that a design is correct, but to verify that the chip has been fabricated as designed, that there are no defective gates or wires. By functional I mean (e.g. in the case of a CPU) to write instructions that exercise most of the combinatorial logic and most of the flip flops on the chip. Often times it takes many millions of test vectors to achieve less than 50% coverage. Which is where scan comes in. A few external pins are needed. All the flip flops in the chip are the wired in series in groups of scan chains. Data can be shifted in serially to the chip via these chains, then the mode switched to exercise the "normal" logic between flip flops, then flipped again and result data can be shifted out of the flip flops and verified by a tester. It's still quite complex, especially when multiple clocks and multiple chains are involved. But it allows for 90%+ test coverage of the logic in a chip without requiring verification engineers to write functional test vectors. Instead, there are tools that automate the process of connecting flip flops in chains and in generating the patterns that exercise the logic between flip flops. The following Wiki touches on the process: https://en.wikipedia.org/wiki/Scan_chain https://en.wikipedia.org/wiki/Scan_chain

wyager 11y ago

That sounds incredibly expensive to route. Every flip flop?

trsohmers 11y ago
It's a process called scan chain insertion. As a chip designer, I can tell you that DFT (Design for Test, which scan chain falls under) can be a real PITA even though the tools are automated. EDIT: Should have also said that it really isn't that big in terms of area... a register plus two wires is nothing in the scheme of things. https://en.wikipedia.org/wiki/Scan_chain https://en.wikipedia.org/wiki/Scan_chain
nhaehnle 11y ago
Kind of, but it's a chain. It works by shifting bits through all flip-flops until they've all "dropped out" of an I/O pin. So you don't need any expensive muxes or crossbars. It's actually one of the largest and most realistic real-world application of TSP and related problems.
PhantomGremlin 11y ago
That sounds incredibly expensive to route. Every flip flop? Almost all ICs nowadays already have scan chains connecting to 99+% of their internal flip flops. This is because it literally has been decades since chips have gotten too complex to do reasonable "functional" tests on chips in production. These tests are used not to verify that a design is correct, but to verify that the chip has been fabricated as designed, that there are no defective gates or wires. By functional I mean (e.g. in the case of a CPU) to write instructions that exercise most of the combinatorial logic and most of the flip flops on the chip. Often times it takes many millions of test vectors to achieve less than 50% coverage. Which is where scan comes in. A few external pins are needed. All the flip flops in the chip are the wired in series in groups of scan chains. Data can be shifted in serially to the chip via these chains, then the mode switched to exercise the "normal" logic between flip flops, then flipped again and result data can be shifted out of the flip flops and verified by a tester. It's still quite complex, especially when multiple clocks and multiple chains are involved. But it allows for 90%+ test coverage of the logic in a chip without requiring verification engineers to write functional test vectors. Instead, there are tools that automate the process of connecting flip flops in chains and in generating the patterns that exercise the logic between flip flops. The following Wiki touches on the process: https://en.wikipedia.org/wiki/Scan_chain https://en.wikipedia.org/wiki/Scan_chain