It's also able to load microcode patches very early on in the machine bring-up process. Microcode can be anywhere as simple as a single hardware enable bit "tur

It's also able to load microcode patches very early on in the machine bring-up process. Microcode can be anywhere as simple as a single hardware enable bit "turn on this hardware unit" or as complex as "this instruction should be decoded as this sequence of microops." It's hard to know exactly what's wrong without more internal, never-to-see-the-light-of-day Intel information, but it's possible the patch is as simple as tweaking the decoding, or disabling an optimization. It's doubtful a fix like this would require disabling an entire instruction set or hardware unit (like the TSX fix required; those are fairly rare bugs, even for Intel). Specifically, given that it happens to be a bug that only happens with FMA3 disabled and hyperthreading enabled, it's probably some kind of hardware scheduling deadlock, and the patch could be as simple as "when the decoder sees this sequence of instructions, add some strategically placed NOPs to avoid the deadlock."