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What are you qualifications in computer architecture? You're arguing against pretty much everyone in the field. > I'm surprised to see a lot of RISC proponents

by wsxcde 11y ago

What are you qualifications in computer architecture? You're arguing against pretty much everyone in the field. > I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is such a good idea. You seem to be implying that there's RISC failed. If you ask anyone who mattered in computer architecture ranging from academics like Patterson who literally wrote the most used books in the field to Intel fellows, they'll all tell you that the essential point the RISC folks were making was proven right. This point being that RISC is requires less logic (=area,power) to implement, it's easier to write compilers for, processors have faster cycle times, and so on. In the end though, it turned out the market valued software compatibility over performance. That, good marketing and a phenomenally efficient supply chain and fab resulted in Intel winning. But don't confuse this with CISC winning or RISC losing. If Intel had to do a clean slate design today, they'd do RISC themselves. In fact, Intel have a few proprietary microcontrollers hidden inside their chipsets and SoCs that were designed post-2005ish and these have RISC architectures. > In my experience, statements like this really mean "it's actually really bad, but we don't want to say that"... after all, who would call benchmarks "controversial" if they were winning? There do tend to be few comparative benchmarks, but here's one that shows how ARM and x86 are competitive, but MIPS is behind in energy efficiency: The benchmark performance depends only on how much effort is put into optimizing the implementation. Intel have on average maybe 200 architects and 200 more designers tweaking their processors for performance for the last 30 years. It is completely absurd to expect a team of 10 or so grad students to compete with them.

userbinator 11y ago
You seem to be implying that there's RISC failed. It did fail to deliver on all its promises. RISC is requires less logic (=area,power) to implement True, but ultimately it is overall energy usage that is important. A tiny low-power CPU with less performance will take longer to complete a task than a larger faster higher-power one, meaning it consumes more energy. That's what the article I linked to shows. processors have faster cycle times That's not necessarily a good thing, as Intel's failed NetBurst microarchitecture shows. Making a CPU with such short delays that it can run at upwards of 10GHz is futile, as power dissipation becomes a huge problem long before that. In fact, Intel have a few proprietary microcontrollers hidden inside their chipsets and SoCs that were designed post-2005ish and these have RISC architectures. If you're referring to the ARC4 in the Management Engine, I have a feeling that was chosen for reasons other than being RISC or otherwise. It is completely absurd to expect a team of 10 or so grad students to compete with them. I remember it said that RISC would be so simple and performant that such small teams could easily design CPUs which vastly outperform the big CISCs at much lower prices, so I don't think it's that absurd of an expectation.

by wsxcde 11y ago

userbinator 11y ago

You seem to be implying that there's RISC failed. It did fail to deliver on all its promises. RISC is requires less logic (=area,power) to implement True, but ultimately it is overall energy usage that is important. A tiny low-power CPU with less performance will take longer to complete a task than a larger faster higher-power one, meaning it consumes more energy. That's what the article I linked to shows. processors have faster cycle times That's not necessarily a good thing, as Intel's failed NetBurst microarchitecture shows. Making a CPU with such short delays that it can run at upwards of 10GHz is futile, as power dissipation becomes a huge problem long before that. In fact, Intel have a few proprietary microcontrollers hidden inside their chipsets and SoCs that were designed post-2005ish and these have RISC architectures. If you're referring to the ARC4 in the Management Engine, I have a feeling that was chosen for reasons other than being RISC or otherwise. It is completely absurd to expect a team of 10 or so grad students to compete with them. I remember it said that RISC would be so simple and performant that such small teams could easily design CPUs which vastly outperform the big CISCs at much lower prices, so I don't think it's that absurd of an expectation.