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Market success != technical merit. However, if you're willing to consider ARM a RISC (well, almost) then there's your market success. Alpha completely dominat

Market success != technical merit. However, if you're willing to consider ARM a RISC (well, almost) then there's your market success. Alpha completely dominated the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC. At the time, x86 compatibility mattered more than it does today. For people designing their own cores for whatever reason (there can be many, research and commercial), RISC-V is very attractive because of all the reasons already given, but it's obviously not the only option. RISC-V is carefully designed compromise; it scales down to extremely cheap cores and up to superscalar. Like Alpha before it, extreme attention has been paid to avoid features/choices that would be bad for OoOE implementations. Some examples: - rs1, rs2, rd fields are always in the same location and all register sources and destinations are explicit (makes decoding faster and you can start fetching/renaming without having decoded) - there are no branch delay slots - instructions produce at most a single result - no condition codes etc (dependencies are explicit) - the sign-bit for all immediate fields is in a fixed location (cheaper sign-extension) and so forth. I'm also a big fan of the conditional branch instruction which unlike the Alpha can compare two registers.

userbinator 11y ago
However, if you're willing to consider ARM a RISC (well, almost) then there's your market success. ARM wasn't really a pure RISC from the beginning (e.g. multicycle instructions like LDM/STM, pre/post-increment addressing modes, built-in shifts), and I'd say the market success, especially more recently, is attributable to the fact that ARM cores are becoming more x86-like. On the other hand, MIPS is the quintessential RISC, and hit as enjoyed some success, but was never really known much for amazing performance or efficiency. I suspect RISC-V will be similar, and all the cheap Chinese tablets/phones/etc. that are currently using MIPS may switch to RISC-V instead, although many are unlicensed clones so cost may not be a factor to them. Alpha completely dominated the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC. Alphas relied primarily on clock frequency to achieve their performance, and were very power-hungry as a result. This is absolutely the RISC philosophy of performance via simpler designs and increasing clock frequency, which stopped being viable long ago. A 200MHz 21064 can do 0.675DMIPS/MHz and consumes 30W, or 0.0225DMIPS/MHz/W; a Pentium (P5) 100MHz has 1.88DMIPS/MHz and consumes 10W, for 0.188DMIPS/MHz/W.
- FullyFunctional 11y ago
  This is getting off-topic, but ARMs success had nothing to do with RISC vs. CISC. It was that _Alpha_ engineers took their skill to the ARM ISA (which at the time had only very weak implementations). They created StrongARM which made people sit up and take notice. Intel ironically inherited the technology and continued developing it under the XScale name. So, yes, Intel in part created their own ARM problem. I feel I have to repeat again that none of this had to do with RISC vs. CISC. It had to do with implementation and market muscle. "Alphas relied primarily on clock frequency to achieve their performance, and were very power-hungry as a result" So was the P4 and it failed, but Intel had enough capital to take a power efficiency clue from Transmeta and turn the ship 180 degrees. What killed the Alpha was three things: delays in getting the new models out, the cost of staying in this game, and of course, the arrival of Itanic. EDIT: An aside: the 64-bit extension of ARM is a completely new and different ISA called AArch64 which incidentally is a lot more RISC-like than the original ARM. IOW, it looks like the ARM designers disagree with you.

userbinator 11y ago

However, if you're willing to consider ARM a RISC (well, almost) then there's your market success. ARM wasn't really a pure RISC from the beginning (e.g. multicycle instructions like LDM/STM, pre/post-increment addressing modes, built-in shifts), and I'd say the market success, especially more recently, is attributable to the fact that ARM cores are becoming more x86-like. On the other hand, MIPS is the quintessential RISC, and hit as enjoyed some success, but was never really known much for amazing performance or efficiency. I suspect RISC-V will be similar, and all the cheap Chinese tablets/phones/etc. that are currently using MIPS may switch to RISC-V instead, although many are unlicensed clones so cost may not be a factor to them. Alpha completely dominated the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC. Alphas relied primarily on clock frequency to achieve their performance, and were very power-hungry as a result. This is absolutely the RISC philosophy of performance via simpler designs and increasing clock frequency, which stopped being viable long ago. A 200MHz 21064 can do 0.675DMIPS/MHz and consumes 30W, or 0.0225DMIPS/MHz/W; a Pentium (P5) 100MHz has 1.88DMIPS/MHz and consumes 10W, for 0.188DMIPS/MHz/W.

FullyFunctional 11y ago
This is getting off-topic, but ARMs success had nothing to do with RISC vs. CISC. It was that _Alpha_ engineers took their skill to the ARM ISA (which at the time had only very weak implementations). They created StrongARM which made people sit up and take notice. Intel ironically inherited the technology and continued developing it under the XScale name. So, yes, Intel in part created their own ARM problem. I feel I have to repeat again that none of this had to do with RISC vs. CISC. It had to do with implementation and market muscle. "Alphas relied primarily on clock frequency to achieve their performance, and were very power-hungry as a result" So was the P4 and it failed, but Intel had enough capital to take a power efficiency clue from Transmeta and turn the ship 180 degrees. What killed the Alpha was three things: delays in getting the new models out, the cost of staying in this game, and of course, the arrival of Itanic. EDIT: An aside: the 64-bit extension of ARM is a completely new and different ISA called AArch64 which incidentally is a lot more RISC-like than the original ARM. IOW, it looks like the ARM designers disagree with you.