4 ms·

How does the GPL prevent those costs from being recovered?

nickpsecurity 11y ago
By allowing anyone to knock off the chip without paying back the R&D. There's already a huge market of counterfeits and clones coming out of China for most things you can think of. It's even easier without reverse engineering: hand design to a fab, individual or MPW, then package and sell the chips. Very little of the price of chips you buy is the material or packaging costs. It's mostly R&D recoup, marketing, administrative, and profit. Most of these companies get all that straight through sales of the chips. Eliminate everything but a tiny margin over physical costs and whats left for further development?
- krupan 11y ago
  "Very little of the price of chips you buy is the material or packaging costs." Are you sure about that? How much markup over material costs is there on most chips?
  - nickpsecurity 11y ago
    I'm not sure on most chips. I do know if you look up MOSIS, etc prices you'll find that most of the cost of the prototyping run is the masks. The masks start at tens of thousands then just go up from there. High-end nodes are in millions to tens of millions. Every prototype run of your chip takes a new mask. Hence, all the money spent on proprietary tooling to reduce odds of digital or physical defects. Many ASIC's still need respins. Then, there's 3rd party stuff like I/O packages. Now, compared to that, the silicon wafer might cost a few grand with packaging (not volume) costing $10-20 a unit. For any OSS project, dare I say most of the cost will be in the first paragraph and recouping it will take significant unit prices. How significant depends on what's being sold and at what volume. A PIC or AVR clone at modest volume will be cheaper than an Oracle T2 clone at low volume. Hope that helps.
  - analognoise 11y ago
    100% sure - once you have the masks, pumping out chips is cheap, if you do it in volume. http://www.adapteva.com/andreas-blog/semiconductor-economics-101/ http://www.adapteva.com/andreas-blog/semiconductor-economics...
    - nickpsecurity 11y ago
      Key quotes: "Super complex SOC platforms like Apple’s Ax family or the IBM Cell very likely exceeded $1B in total development costs and involved thousands of engineers in aggregate." "Meanwhile relatively simple SOCs like the Epiphany family of chips were designed for less than $3M over the span of 3 years.[1,2]" And Adapteva did such a good job being cheaper than average they wrote a [different] blog post about how they went about it. So, the low end was $3 million over 3 years while users wanting to ditch proprietary are asking for price/performance/watts closer to the above quote that cost $1 billion. Hence, my prediction it will take millions to tens of millions to make something acceptable. Also, me pushing Cavium's model of RISC multicore + HW accelerators for common things. I think it will help by taking load (& optimization) off the main CPU's. Now, people doing analog stuff have it a lot easier given even 350nm is often good for that. That stuff can get really cheap: http://www.planetanalog.com/author.asp?section_id=526&doc_id=559519 http://www.planetanalog.com/author.asp?section_id=526&doc_id...
  - adapteva 11y ago
    There is no typical...but here are some guidelines 1.2x (companies are either ultra efficient, copycats, suicidal, or dumping) 2x (US companies shipping volume, healthy) 4x (goal for FPGA companies and mixed signal niche) 10x (goal for companies with monopolies) 100x (one-offs, like processors for military/satellite)
    - nickpsecurity 11y ago
      I like that breakdown. That sounds about right. Especially the FPGA's and military. :) Btw, I'd love a hardware engineeer's take on my idea for bootstrapping open hardware. The idea is HW development issues make it too costly. Led me to consider an open-source FPGA on 45nm or below with tool-chain. Let academics build (and open) the hardest stuff with non-profit integrating that with I/O and other key I.P. onto small number of chips selling it at cost. Example open FGPA (a start, not end-goal) http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.pdf http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43... Example open-flow (add VPR or whatever FPGA tool is called) http://opencircuitdesign.com/qflow/ http://opencircuitdesign.com/qflow/ Idea is we get an easy FPGA set up to allow targeting with open or commercial tools. Its specs are open for review and enhancement. There is a via- or metal-configurable S-ASIC co-developed that matches its architecture. Like with eASIC, people can do an inexpensive conversion if they choose. Even considered using people they turned down in their contest (but whose stuff worked) to build the tooling for that. ;) So, you have cheap-as-possible 45nm or below FPGA's being cranked out with more I.P. and tooling all the time. S-ASIC conversion is inexpensive due to matched architecture. If designed for it in mind, ASIC conversion wouldn't be too difficult either for FPGA-proven designs given staff and tooling. The HW cost is essentially some important cells, NOC, key IP (eg USB, PCI, DDR), memories, some analog, and at least one integration. With MPW's & academic support, it might cost a fraction of what it otherwise would. Not going to be EDA or HW competitive with Xilinx or Altera but not $600-$2,000 a chip w/ closed bitstream either. My main worry outside market demand is effect of patent suits, esp if they demand royalties per unit. Otherwise, I'm hoping combo of academics, existing tooling, open FPGA's, and S-ASIC's is a solid combo for a start on widely-accessible, open HW. Still getting feedback from HW pro's before I start knocking on doors, though.

By allowing anyone to knock off the chip without paying back the R&D. There's already a huge market of counterfeits and clones coming out of China for most things you can think of. It's even easier without reverse engineering: hand design to a fab, individual or MPW, then package and sell the chips. Very little of the price of chips you buy is the material or packaging costs. It's mostly R&D recoup, marketing, administrative, and profit. Most of these companies get all that straight through sales of the chips. Eliminate everything but a tiny margin over physical costs and whats left for further development?

krupan 11y ago
"Very little of the price of chips you buy is the material or packaging costs." Are you sure about that? How much markup over material costs is there on most chips?
- nickpsecurity 11y ago
  I'm not sure on most chips. I do know if you look up MOSIS, etc prices you'll find that most of the cost of the prototyping run is the masks. The masks start at tens of thousands then just go up from there. High-end nodes are in millions to tens of millions. Every prototype run of your chip takes a new mask. Hence, all the money spent on proprietary tooling to reduce odds of digital or physical defects. Many ASIC's still need respins. Then, there's 3rd party stuff like I/O packages. Now, compared to that, the silicon wafer might cost a few grand with packaging (not volume) costing $10-20 a unit. For any OSS project, dare I say most of the cost will be in the first paragraph and recouping it will take significant unit prices. How significant depends on what's being sold and at what volume. A PIC or AVR clone at modest volume will be cheaper than an Oracle T2 clone at low volume. Hope that helps.
- analognoise 11y ago
  100% sure - once you have the masks, pumping out chips is cheap, if you do it in volume. http://www.adapteva.com/andreas-blog/semiconductor-economics-101/ http://www.adapteva.com/andreas-blog/semiconductor-economics...
  - nickpsecurity 11y ago
    Key quotes: "Super complex SOC platforms like Apple’s Ax family or the IBM Cell very likely exceeded $1B in total development costs and involved thousands of engineers in aggregate." "Meanwhile relatively simple SOCs like the Epiphany family of chips were designed for less than $3M over the span of 3 years.[1,2]" And Adapteva did such a good job being cheaper than average they wrote a [different] blog post about how they went about it. So, the low end was $3 million over 3 years while users wanting to ditch proprietary are asking for price/performance/watts closer to the above quote that cost $1 billion. Hence, my prediction it will take millions to tens of millions to make something acceptable. Also, me pushing Cavium's model of RISC multicore + HW accelerators for common things. I think it will help by taking load (& optimization) off the main CPU's. Now, people doing analog stuff have it a lot easier given even 350nm is often good for that. That stuff can get really cheap: http://www.planetanalog.com/author.asp?section_id=526&doc_id=559519 http://www.planetanalog.com/author.asp?section_id=526&doc_id...
- adapteva 11y ago
  There is no typical...but here are some guidelines 1.2x (companies are either ultra efficient, copycats, suicidal, or dumping) 2x (US companies shipping volume, healthy) 4x (goal for FPGA companies and mixed signal niche) 10x (goal for companies with monopolies) 100x (one-offs, like processors for military/satellite)
  - nickpsecurity 11y ago
    I like that breakdown. That sounds about right. Especially the FPGA's and military. :) Btw, I'd love a hardware engineeer's take on my idea for bootstrapping open hardware. The idea is HW development issues make it too costly. Led me to consider an open-source FPGA on 45nm or below with tool-chain. Let academics build (and open) the hardest stuff with non-profit integrating that with I/O and other key I.P. onto small number of chips selling it at cost. Example open FGPA (a start, not end-goal) http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.pdf http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43... Example open-flow (add VPR or whatever FPGA tool is called) http://opencircuitdesign.com/qflow/ http://opencircuitdesign.com/qflow/ Idea is we get an easy FPGA set up to allow targeting with open or commercial tools. Its specs are open for review and enhancement. There is a via- or metal-configurable S-ASIC co-developed that matches its architecture. Like with eASIC, people can do an inexpensive conversion if they choose. Even considered using people they turned down in their contest (but whose stuff worked) to build the tooling for that. ;) So, you have cheap-as-possible 45nm or below FPGA's being cranked out with more I.P. and tooling all the time. S-ASIC conversion is inexpensive due to matched architecture. If designed for it in mind, ASIC conversion wouldn't be too difficult either for FPGA-proven designs given staff and tooling. The HW cost is essentially some important cells, NOC, key IP (eg USB, PCI, DDR), memories, some analog, and at least one integration. With MPW's & academic support, it might cost a fraction of what it otherwise would. Not going to be EDA or HW competitive with Xilinx or Altera but not $600-$2,000 a chip w/ closed bitstream either. My main worry outside market demand is effect of patent suits, esp if they demand royalties per unit. Otherwise, I'm hoping combo of academics, existing tooling, open FPGA's, and S-ASIC's is a solid combo for a start on widely-accessible, open HW. Still getting feedback from HW pro's before I start knocking on doors, though.