Maybe that's a dumb question but why should this chip be highly parallel? In the case of GPU computations are by their nature embarrassingly parallel but I don'

Maybe that's a dumb question but why should this chip be highly parallel? In the case of GPU computations are by their nature embarrassingly parallel but I don't see why this should be the case for SPU. Why not just add a few more CPU cores and let this specialized controller handle the problem of concurrent accesses?