2 ms·

Thanks for the information. I understand its a hard problem but an essential one that needs a solution. It needs to be supported both in Chisel and with appropr

• _chris_ 11y ago
  > Is there any one in the community who is actively working on the verification story ? Not sure. I'd look out for videos to show up at the RISC-V workshop that's ongoing (http://riscv.org/workshop-jan2016.html http://riscv.org/workshop-jan2016.html). The problem is verification is where the $$$ is, so even amongst people sharing their CPU source code, they're less willing to share the true value-provided of their efforts. A debug spec is being developed and will be added to Rocket-chip to make this problem easier. With that said, MIT gave a good talk at the RISC-V workshop about their works on verification, and we open sourced our torture tester at (http://riscv.org/workshop-jan2016.html http://riscv.org/workshop-jan2016.html).
  • _chris_ 11y ago
    https://github.com/ucb-bar/riscv-torture https://github.com/ucb-bar/riscv-torture, stupid copy/paste.