> OpenRISC, OpenSPARC Can't really comment, since these aren't our projects. I haven't really seen any developments on these fronts, though. > RISC-V, Z-Scale

> OpenRISC, OpenSPARC Can't really comment, since these aren't our projects. I haven't really seen any developments on these fronts, though. > RISC-V, Z-Scale, BOOM RISC-V is the ISA. Rocket, Z-Scale, and BOOM are implementations of the ISA we've produced at Berkeley. Rocket is our reference implementation. It is a 64-bit in-order core. Z-scale is a small 32-bit core with no MMU intended for microcontrollers. BOOM is an out-of-order 64-bit core. They all share some common code, but BOOM is a bit behind the other two. We have taped out different Rocket and Z-scale chips. But these run as tethered systems and were only meant for our research. As a university research lab, we do not really have any intentions for mass manufacture. ASB can answer better about when lowRISC chips will be commercially available.