This has been discussed before in the RISC-V community. See https://lists.riscv.org/lists/arc/hw-dev/2014-09/msg00007.html https://lists.riscv.org/lists/arc/hw-

This has been discussed before in the RISC-V community. See https://lists.riscv.org/lists/arc/hw-dev/2014-09/msg00007.html https://lists.riscv.org/lists/arc/hw-dev/2014-09/msg00007.ht... (sorry, you'll probably have to click the "I'm not a spammer link" first time and then load the link again - the riscv mailing lists seem to use the most painful mailing list software and Gmane wasn't archiving the riscv lists at that time). One reason for push-back on implicit overflow checking is that it complicates superscalar designs by adding another exception source. The good news is that with an open ISA like RISC-V with high quality reference implementations, we can finally actually perform meaningful experiments to test these assumptions - adding different overflow checking semantics to a realistic implementation, quantifying the difference when putting it through the ASIC flow for a real process and making the matching changes to the compiler. It seems ridiculous that us in the computer architecture community haven't had the ability before.