3 ms·

This sounds really interesting. I don't know what too much of this means though. Can you recommend books or in depth articles about the process of ic making?

nickpsecurity 11y ago
The Wikipedia articles on semiconductor manufacturing are pretty good. Far as ASIC's, I struggled a while to find a great resource on all aspects of design, verification, and prototyping. Here's the best one I found for you: http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/EDA_Chapter1.pdf http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/EDA_Chapter1.pdf On top of that, there's the cost of the photomasks that print the samples for testing (and later production). They range from tens of thousands on oldest nodes to millions on newer ones. Every time you screw up and change the design you buy another mask. Hence, avoidance of new nodes by low volume groups, design/verification tools that can cost $1mil/yr a person, and heavy re-use of components. One trick that's popular is called multi-project wafers: a mask and chip run that's shared by several people with high cost split among them. This is available through groups like MOSIS and X-Fab. Lets you test your design in [more] affordable pieces. Plus, tooling and overall cost has come down for older nodes which are still highly usable for many scenarios: http://gsaglobal.org/forum/2009/1/articles_full_double.asp http://gsaglobal.org/forum/2009/1/articles_full_double.asp Open tools are getting there slowly but not reliable or competitive enough. Here's the only open flow I know of: http://opencircuitdesign.com/qflow/ http://opencircuitdesign.com/qflow/ So, overall barrier to entry for ASIC design is expensive expertise, high-cost of proprietary tools, and cost of masks (or MPW's). Going cheap on all these still gives several hundred thousand for a useful design on a good node. Simpler, single-purpose chips on oldest nodes can be less than that, though. Here's an example: http://www.planetanalog.com/author.asp?section_id=526&doc_id=559519 http://www.planetanalog.com/author.asp?section_id=526&doc_id... Hope all this helps your understanding of the situation.

nickpsecurity 11y ago

The Wikipedia articles on semiconductor manufacturing are pretty good. Far as ASIC's, I struggled a while to find a great resource on all aspects of design, verification, and prototyping. Here's the best one I found for you: http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/EDA_Chapter1.pdf http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/EDA_Chapter1.pdf On top of that, there's the cost of the photomasks that print the samples for testing (and later production). They range from tens of thousands on oldest nodes to millions on newer ones. Every time you screw up and change the design you buy another mask. Hence, avoidance of new nodes by low volume groups, design/verification tools that can cost $1mil/yr a person, and heavy re-use of components. One trick that's popular is called multi-project wafers: a mask and chip run that's shared by several people with high cost split among them. This is available through groups like MOSIS and X-Fab. Lets you test your design in [more] affordable pieces. Plus, tooling and overall cost has come down for older nodes which are still highly usable for many scenarios: http://gsaglobal.org/forum/2009/1/articles_full_double.asp http://gsaglobal.org/forum/2009/1/articles_full_double.asp Open tools are getting there slowly but not reliable or competitive enough. Here's the only open flow I know of: http://opencircuitdesign.com/qflow/ http://opencircuitdesign.com/qflow/ So, overall barrier to entry for ASIC design is expensive expertise, high-cost of proprietary tools, and cost of masks (or MPW's). Going cheap on all these still gives several hundred thousand for a useful design on a good node. Simpler, single-purpose chips on oldest nodes can be less than that, though. Here's an example: http://www.planetanalog.com/author.asp?section_id=526&doc_id=559519 http://www.planetanalog.com/author.asp?section_id=526&doc_id... Hope all this helps your understanding of the situation.