3 ms·

> The photonic I/O on the chip is also energy-efficient, using only 1.3 picojoules per bit, equivalent to consuming 1.3 watts of power to transmit a terabit of

by yelnatz 11y ago

> The photonic I/O on the chip is also energy-efficient, using only 1.3 picojoules per bit, equivalent to consuming 1.3 watts of power to transmit a terabit of data per second. In the experiments, the data was sent to a receiver 10 meters away and back. They mentioned this, but didn't compare it to classic electrical chips. Does anyone know what we have now?

renox 11y ago
It's difficult to compare as for optical you have to add the power usage of the laser itself and for the electrical chips you may need repeaters (as stated in the article) depending on the length and bandwith used.
exDM69 11y ago
> Does anyone know what we have now? I can't quote exact figures but to give a ballpark figure, we're talking about ~5 picojoules per bit at a distance of less than 10 millimeters. This is on a modern (20 nm) SoC. So we're talking about a pretty significant improvement in power consumption and communication distances. A modern chip running at 2-4 GHz requires several clock cycles for a bit to reach from one corner of the silicon to another. It's becoming a major hurdle to think about when designing chips.
- thecopy 11y ago
  Does this imply that it will be possible to increase the clock-speed 5/1.3=3.8 times and still be able to cool the CPU with basic air-cooling?
  - exDM69 11y ago
    No, I don't think so. I don't think that light can be used to replace all (metal) conductors on a silicon chip, at least in the near term. However, this technology has the potential of bringing performance gains to on-chip memories such as L1 and L2 caches as well as software configurable scratch pad memory. Other possibilities that spring to mind are faster core-to-core communications as well as bundling more cores on a same die as the faster communication makes physically larger dies possible. disclaimer: I work in the semiconductor industry but this is not my area of expertise, my speculation is as good as anyone else's.
  - typon 11y ago
    No it doesn't. This does not affect clock frequency on a single CPU. This would improve bandwidth and latency in I/O with off chip circuitry such as memory or co-processors (like GPU).
    - madengr 11y ago
      Why would it improve latency? At most it would reduce it by half; i.e. Free-space propagation vs traces buried in FR4.
      - typon 11y ago
        It wouldn't and you're correct. I don't know why I wrote that. Sorry!
trsohmers 11y ago
Modern 12.5 and 28 gigabit SerDes are around 15 to 20 picojoules per bit when being used for something like PCIe3 over your standard FR4 PCB traces, while longer distance (like the linked work) is in the 30pJ/bit range. 1.3 picojoules/bit is a hug advancement, as the only things that get that low are over very short distances (I am working with a brand new SerDes for multi chip module communication that has an amazing 1pJ/bit, but only up to ~24mm).

by yelnatz 11y ago

renox 11y ago

It's difficult to compare as for optical you have to add the power usage of the laser itself and for the electrical chips you may need repeaters (as stated in the article) depending on the length and bandwith used.

exDM69 11y ago

> Does anyone know what we have now? I can't quote exact figures but to give a ballpark figure, we're talking about ~5 picojoules per bit at a distance of less than 10 millimeters. This is on a modern (20 nm) SoC. So we're talking about a pretty significant improvement in power consumption and communication distances. A modern chip running at 2-4 GHz requires several clock cycles for a bit to reach from one corner of the silicon to another. It's becoming a major hurdle to think about when designing chips.

thecopy 11y ago
Does this imply that it will be possible to increase the clock-speed 5/1.3=3.8 times and still be able to cool the CPU with basic air-cooling?
- exDM69 11y ago
  No, I don't think so. I don't think that light can be used to replace all (metal) conductors on a silicon chip, at least in the near term. However, this technology has the potential of bringing performance gains to on-chip memories such as L1 and L2 caches as well as software configurable scratch pad memory. Other possibilities that spring to mind are faster core-to-core communications as well as bundling more cores on a same die as the faster communication makes physically larger dies possible. disclaimer: I work in the semiconductor industry but this is not my area of expertise, my speculation is as good as anyone else's.
- typon 11y ago
  No it doesn't. This does not affect clock frequency on a single CPU. This would improve bandwidth and latency in I/O with off chip circuitry such as memory or co-processors (like GPU).
  - madengr 11y ago
    Why would it improve latency? At most it would reduce it by half; i.e. Free-space propagation vs traces buried in FR4.
    - typon 11y ago
      It wouldn't and you're correct. I don't know why I wrote that. Sorry!

trsohmers 11y ago

Modern 12.5 and 28 gigabit SerDes are around 15 to 20 picojoules per bit when being used for something like PCIe3 over your standard FR4 PCB traces, while longer distance (like the linked work) is in the 30pJ/bit range. 1.3 picojoules/bit is a hug advancement, as the only things that get that low are over very short distances (I am working with a brand new SerDes for multi chip module communication that has an amazing 1pJ/bit, but only up to ~24mm).