4 ms·
50x isn't unreasonable if you can parallelize and/or pipeline a rigidly-defined process, cutting out as much memory and cache accesses as possible. With the ri
by koko775 11y ago
50x isn't unreasonable if you can parallelize and/or pipeline a rigidly-defined process, cutting out as much memory and cache accesses as possible.
With the right programming model, 50x seems very, very reasonable, not even magical. A typical computer does a decently high amount of context-switching and cache-loading.
- revelation 11y agoYes, of course. Hence why FPGAs are brilliant for stuff like networking equipment, massively parallel coupled with massive low-level IO. But it doesn't work that way for arbitrary algorithms.
- koko775 11y agoOn the contrary, given a capable compiler and/or language, translating algorithms into hardware sounds extremely feasible to me.
- nickpsecurity 11y agoIt's easy in theory but hard go do well. Most that work pretty well are commercial. Here's the only OSS one I know still getting significant: http://legup.eecg.utoronto.ca/publications.php http://legup.eecg.utoronto.ca/publications.php
- koko775 11y agoI think then we are in agreement that it is /feasible/, then? I imagine an FPGA in every chipset would go a long way towards writing the software to put them to practical use, though that may also be wishful thinking on my part.
- nickpsecurity 11y agoIt was mainly used for algorithms and prototyping ASIC's for most of its existence. The high level tools advertised to software people likewise did that. These days, they have great I/O options too.