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Open Source FPGA Toolchain Builds CPU
- placeybordeaux 11y agoI always thought the advantage of a FPGA is that they are very fast when programmed for a specific task. This seems like an interesting project, but is there a case where this would be preferred over any given CPU?
- blackguardx 11y agoYou can add instructions on the fly or switch CPU architectures on the fly. Go from a MIPS clone to an ARM clone. The main advantage of FPGAs is flexibility.
- nickpsecurity 11y agoFlexibility and lower development costs. ASIC developments cost hundreds of thousands to tens of millions. FPGA's give you low development cost but relatively-high, unit price.
- vvanders 11y agoAlso at a higher power usage as well.
- nickpsecurity 11y agoYes. There's been good work in that space to make some of them use hardly any power where unnecessary and asynchronous ones (eg Achronix) could take it even further. Yet, always will be behind on ASIC's on power usage. I don't see them getting around that.
- ZenoArrow 11y agoThere's also the idea of 'baked' FPGA's, which are a middle ground in performance between FPGAs and ASICs, but at a much lower cost than ASICs. EDIT: Looks like Altera no longer offers the HardCopy option, do any of its competitors offer something similar? https://www.altera.com/products/general/asic.smartphone.html https://www.altera.com/products/general/asic.smartphone.html
- nickpsecurity 11y agoYou're thinking of Structured ASIC's: FPGA-like devices that are configured by via's or metal layers. They knock some layers and material issues off the design, lowering costs. They use less power, are faster, and have lower unit costs than FPGA's. So, it seems win win. They primarily didn't take off because lower-cost tooling and multi-project wafers made low-end ASIC's cheaper than before. Still a good option to consider if ramping up volume on a FPGA-proven design. I've always said best thing to do for open-hardware is a matching 45-90nm FPGA and S-ASIC architecture with plenty of pre-proven blocks (esp I/O and memory). Anyway, here's you a list of some for your own research. eASIC is longest running plus has ability to prototype chips for you without mask costs. That's awesome. Triad is extending concept to analog/mixed-signal at about $400k a projects last I heard. Others I know nothing about. http://www.easic.com/products/90-nm-easic-nextreme/ http://www.easic.com/products/90-nm-easic-nextreme/ Note: They have Nextreme down to 28nm (!!!) plus an ASIC conversion. http://www.triadsemi.com/reconfigurable-full-custom-asic/ http://www.triadsemi.com/reconfigurable-full-custom-asic/ http://www.gigoptix.com/products/asics/asic-type/structured-asic/ http://www.gigoptix.com/products/asics/asic-type/structured-... http://www.micro-rdc.com/Products%20Structured%20ASIC.htm http://www.micro-rdc.com/Products%20Structured%20ASIC.htm
- 0xcde4c3db 11y agoXilinx advertises "EasyPath" as an ASIC alternative, but I'm pretty sure that's just a form of cost reduction for the exact same FPGA chips (by enabling them to use defective chips where the specified bitstream doesn't hit the defect?) rather than an actual "hard" option.
- nickpsecurity 11y ago
- zokier 11y agoI think the typical use-case for general purpose CPU cores in FPGAs is for all sorts of random bookkeeping/scaffolding to support the main custom logic, for example handling the UI or something like that. Kinda contrived analogy would be that while SQL is good for getting data from DB you still usually want to hand over the data to some more general purpose language app for display or whatnot.
- detaro 11y agoYou often need CPUs to control other, fast parts you can only implement in the FPGA. Then it often is easier to implement a CPU in the FPGA, rather than connecting an external CPU to the FPGA, because you can integrate them better (by adding instructions to the CPU, or have it share memory, not having to worry about getting signal across limited IO pins, easily running everything on the same clock, ...)
- etiam 11y agoFrom my understanding it's a promising path towards a free, verifiable processor. FPGA:s apparently are simple and repetitive enough that it's feasible to verify their structure by X-ray, and the configuration is under user control. So while I doubt they would be able to compete on performance in most cases, it could offer access to a real rarity: A CPU that can really be known and trusted.
- sklogic 11y agoSoft CPU cores are often used as parts of larger designs, e.g., for managing communications with the rest of the world, or to run the core algorithm and accelerate the execution using custom instructions.
- nickpsecurity 11y agoIt would be interesting to see someone put JOP on FPGA through the toolchain: http://www.jopdesign.com/ http://www.jopdesign.com/ Then maybe academics in INFOSEC can try to put JX OS on it for secure, embedded apps: http://www4.cs.fau.de/Projects/JX/ http://www4.cs.fau.de/Projects/JX/ Native Java means no breaking out of JVM's model down to weird native code.
- sklogic 11y agoIcestorm and yosys are cool! Since then even more CPUs are working on ICE40: https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32 Or a really small and slow one (smaller than J1, but needs more RAM): https://github.com/combinatorylogic/soc/tree/master/backends/tiny1 https://github.com/combinatorylogic/soc/tree/master/backends...
- listic 11y agoBut does it use an open source toolchain? Also, where does it say that it runs on ICE40?
- bri3d 11y agoPicoRV32 absolutely runs on iCE40 and the open toolchain. Check out scripts/icestorm and http://www.clifford.at/papers/2015/yosys-icestorm-etc/slides.pdf http://www.clifford.at/papers/2015/yosys-icestorm-etc/slides...
- gluggymug 11y agoThe target is the iCE40 HX8K according to the slides (p17) not the icestick unfortunately. It uses 1521 LUTs with Yosys. The icestick is a HX1K which has 1280 LUTs I think.
- ZenoArrow 11y agoDoes the PicoRV32 make use of Xilinx-only features?
- grandalf 11y agoI was looking at IceStick kits the other day and they appear to be backordered > 11 weeks.
- cottonseed 11y agoMouser has expected delivery date mid-January.
- verbify 11y agoWhy are they so popular?
- ZenoArrow 11y agoThe FPGA used (iCE40) is the only one currently on the market with a fully open-source toolchain, and the IceStick is among the cheapest boards for experimenting with the iCE40.
- Gracana 11y agoOh wow, a few weeks ago I bought one on digikey for kicks because of this project, I guess a lot of folks are doing the same.
- xellisx 11y agoI bought one a while back ago, then I realized the number of I/O's was very low for what I wanted to do. Would have been nice to have access to all the 95 I/O's of the iCE40HX-1K instead of just 16 (or is it 26?)
- grandalf 11y agoI agree. The FleaFPGA has GPIO IO but still not all the IOs. http://www.fleasystems.com/fleaFPGA.html http://www.fleasystems.com/fleaFPGA.html
- ZenoArrow 11y agoWill put this here just in case anyone is interested, it's a FPGA Hat for the Raspberry Pi, based on the iCE40 FPGA. https://github.com/xesscorp/CAT-Board/blob/master/README.md https://github.com/xesscorp/CAT-Board/blob/master/README.md