That's not quite right - his example models execution as one thread at a time, switching on a cache miss because most of the extra work that gets done by SMT is

That's not quite right - his example models execution as one thread at a time, switching on a cache miss because most of the extra work that gets done by SMT is when you get a cache miss, freeing up the rest of the processor. While extra work can also be done when there isn't a stall (for example, when the processor is unable to sufficiently parallelise execution of the one thread), his argument is that this is a relatively insignificant fraction of the gain produced by HT, so his model is sufficiently accurate. Now, I don't know practically whether this is true or not, but ulrich drepper ought to :-).