What (I think) I know of the subject: For a resolution of "1920 x 1080 @ 60Hz" the FPGA needs to run only at the pixel clock's frequency, which is "only" 124.4

What (I think) I know of the subject: For a resolution of "1920 x 1080 @ 60Hz" the FPGA needs to run only at the pixel clock's frequency, which is "only" 124.416 MHz (1920x1080x60 / (10^6)). Then on every pixel clock cycle, the FPGA needs to present each bit of what makes-up-a-pixel on it's output pins. In case of 24bpp, that would require 24 dedicated output pins. In addition, a dedicated DVI transmitter chip would be required to serialize and encode that 24 wide bus to those DVI-compliant three differential signal lines in addition to doing the 8b/10b encoding. Roughly. Or the FPGA could have a high-speed serializer built-it which could replace the dedicated chip. ~sigh~ I wish I knew enought about electronics to play around designing such a serializer, it tickles my fancy :)