6 ms·

Common FPGAs are limited to sup-GHz speeds. Common DACs (afaik) are parallel, letting them be driven at lower clock speeds than equivalent serial digital device

Common FPGAs are limited to sup-GHz speeds. Common DACs (afaik) are parallel, letting them be driven at lower clock speeds than equivalent serial digital devices. 1920 x 1080 x 24bpp x (10/8 due to TMDS 8b/10b encoding) 60hz ~= 3.5 gigabits a second, / 3 (3 data lines in DVI/HDMI) = just over a gigabit per data line, plus surely some overhead that I don't know about. I'm not an EE but it sounds like it would be hard to generate a >1GHz signal on a <1GHz FPGA. Whereas with an analog signal driven by 3 8-bit DACs, you're dealing just dealing with 1920 x 1080 x (VGA overhead) * 60hz = a 120~ megahertz signal that can easily be generated by any FPGA. (the 24bpp is irrelevant because it is being transferred in parallel)

gima 11y ago
What (I think) I know of the subject: For a resolution of "1920 x 1080 @ 60Hz" the FPGA needs to run only at the pixel clock's frequency, which is "only" 124.416 MHz (1920x1080x60 / (10^6)). Then on every pixel clock cycle, the FPGA needs to present each bit of what makes-up-a-pixel on it's output pins. In case of 24bpp, that would require 24 dedicated output pins. In addition, a dedicated DVI transmitter chip would be required to serialize and encode that 24 wide bus to those DVI-compliant three differential signal lines in addition to doing the 8b/10b encoding. Roughly. Or the FPGA could have a high-speed serializer built-it which could replace the dedicated chip. ~sigh~ I wish I knew enought about electronics to play around designing such a serializer, it tickles my fancy :)
- rjsw 11y ago
  The Parallella board has an HDMI transmitter connected to the FPGA, it uses the same generation of FPGA as the Mega65 that is described elsewhere in the thread.
pjc50 11y ago
It's not even that high resolution. https://github.com/mist-devel/mist-board/wiki/Displays https://github.com/mist-devel/mist-board/wiki/Displays Remember the original hardware being emulated targeted PAL TVs: 576 lines @ 50Hz. Lower resolution HDMI is certainly feasible, but you have to care more about the signal integrity when designing the board, and it's harder to debug: http://www.fpga4fun.com/HDMI.html http://www.fpga4fun.com/HDMI.html
- wannabeehwdev 11y ago
  True, but the upscaling hardware in most monitors and especially TVs sucks and adds extra frame(s) of latency, so ideally you'd upscale the picture on the FPGA to the display's native resolution (or at least something common like 1080p) to get the best quality (pixel doubling if possible) and lowest latency (a scanline or two) possible. Something I didn't consider when I posted was that a lot of people will want to use this with a VGA CRT, especially since there is lots of Amiga software (including the Workbench itself) that changes the pixel clock midframe, which would pretty much require upscaling hardware to produce a signal that a modern LCD would accept. VGA+a CRT requirement becomes a much simpler solution in light of this.

gima 11y ago

What (I think) I know of the subject: For a resolution of "1920 x 1080 @ 60Hz" the FPGA needs to run only at the pixel clock's frequency, which is "only" 124.416 MHz (1920x1080x60 / (10^6)). Then on every pixel clock cycle, the FPGA needs to present each bit of what makes-up-a-pixel on it's output pins. In case of 24bpp, that would require 24 dedicated output pins. In addition, a dedicated DVI transmitter chip would be required to serialize and encode that 24 wide bus to those DVI-compliant three differential signal lines in addition to doing the 8b/10b encoding. Roughly. Or the FPGA could have a high-speed serializer built-it which could replace the dedicated chip. ~sigh~ I wish I knew enought about electronics to play around designing such a serializer, it tickles my fancy :)

rjsw 11y ago
The Parallella board has an HDMI transmitter connected to the FPGA, it uses the same generation of FPGA as the Mega65 that is described elsewhere in the thread.

pjc50 11y ago

It's not even that high resolution. https://github.com/mist-devel/mist-board/wiki/Displays https://github.com/mist-devel/mist-board/wiki/Displays Remember the original hardware being emulated targeted PAL TVs: 576 lines @ 50Hz. Lower resolution HDMI is certainly feasible, but you have to care more about the signal integrity when designing the board, and it's harder to debug: http://www.fpga4fun.com/HDMI.html http://www.fpga4fun.com/HDMI.html

wannabeehwdev 11y ago
True, but the upscaling hardware in most monitors and especially TVs sucks and adds extra frame(s) of latency, so ideally you'd upscale the picture on the FPGA to the display's native resolution (or at least something common like 1080p) to get the best quality (pixel doubling if possible) and lowest latency (a scanline or two) possible. Something I didn't consider when I posted was that a lot of people will want to use this with a VGA CRT, especially since there is lots of Amiga software (including the Workbench itself) that changes the pixel clock midframe, which would pretty much require upscaling hardware to produce a signal that a modern LCD would accept. VGA+a CRT requirement becomes a much simpler solution in light of this.