I was in a 3DIC research group for ~2 years. We were mainly trying to build heat models for stacked chip designs to investigate this issue. Another group that

I was in a 3DIC research group for ~2 years. We were mainly trying to build heat models for stacked chip designs to investigate this issue. Another group that was looking at architecture was primarily relying on placing low power density devices on the lower levels of the chip (with worse heat dissipation) and the high-power devices at the top (with better heat dissipation), though I never saw the results of their finished design. Ultimately though, heat is the primary issue with 3DIC. Assuaging the memory bottleneck by drastically increasing bandwidth at the cost of significantly more heat.