Transmeta is more a traditional VLIW processor which is a bit different in some ways that EPIC. On an Itanium you're indicating to the chips that these N instr

Transmeta is more a traditional VLIW processor which is a bit different in some ways that EPIC. On an Itanium you're indicating to the chips that these N instructions can take place on the same clock cycle (even if they're spread out across multiple cycles in theory) and there are some nifty tricks with trying to reduce memory latency variability. Transmeta had what's known as an exposed pipeline VLIW design. If you tell the multiplier to do it's thing and put the result in Register 6 then you can still read the previous value from register 6 until the multiplication is done. So you always need to recompile for each version of the hardware.