4 ms·
Note that his example is about a processor that can only execute one thread at a time, switching on a cache miss. This is not SMT. The main problem is if the w
by grogers 17y ago
Note that his example is about a processor that can only execute one thread at a time, switching on a cache miss. This is not SMT.
The main problem is if the working set size of the single threaded code fits just in cache, but the combined working set size of both threads does not. In this case the threads are competing for the shared L1 cache instead of doing useful work.
- AlisdairO 17y agoThat's not quite right - his example models execution as one thread at a time, switching on a cache miss because most of the extra work that gets done by SMT is when you get a cache miss, freeing up the rest of the processor. While extra work can also be done when there isn't a stall (for example, when the processor is unable to sufficiently parallelise execution of the one thread), his argument is that this is a relatively insignificant fraction of the gain produced by HT, so his model is sufficiently accurate. Now, I don't know practically whether this is true or not, but ulrich drepper ought to :-).