4 ms·
I'm fairly sure E5520 has 32 kB L1 data cache, not 128 kB. L1 caches are core local, not shared like L3.
by vardump 11y ago
I'm fairly sure E5520 has 32 kB L1 data cache, not 128 kB. L1 caches are core local, not shared like L3.
- vidarh 11y agoThis is what the datasheet says [1]: - Instruction Cache = 32kB, per core - Data Cache = 32kB, per core - 256kB Mid-Level cache, per core - 8MB shared among cores (up to 4) So I guess the confusion is that Intel moved the L2 cache onto each core (from Nehalem onwards, I think?) and used that opportunity to substantially lower latency for it. [1] http://www.intel.com/content/www/us/en/processors/xeon/xeon-5500-vol-1-datasheet.html http://www.intel.com/content/www/us/en/processors/xeon/xeon-...