How would one, practically, go about modeling the impact of L3 impact in a SoC design, assuming you were intending to produce sonething like the A9X? (I speak

How would one, practically, go about modeling the impact of L3 impact in a SoC design, assuming you were intending to produce sonething like the A9X? (I speak as one who loved sim_g4 as a modeling tool for verifying compiler efficiency, or rather, occasional lack thereof. So easy to see when a cache miss would occur, or just execution unit contention)