>The ARM peripherals need to be assigned to I/O pins which happens in the FPGA (PL in Zynq terms). ARM "hard" peripherals can be assigned to MIO pins, which ha

>The ARM peripherals need to be assigned to I/O pins which happens in the FPGA (PL in Zynq terms). ARM "hard" peripherals can be assigned to MIO pins, which have nothing to do with the PL, or EMIO which can be routed through PL to the FPGA pins. In both cases, the user must write to PS registers to configure internal muxes and assign the peripheral to a given set of pins. In the latter you must assign the ARM pin as an input in the PL and route it to a PL output as in any regular FPGA design. >The ARM subsystem has bus connections to programmable logic which happens entirely in the FPGA (e.g., you connect a 16550 UART to the ARM via AXI bus, etc). Yes it has but the interconnect subsystem is configured in software not through the bitsream. > I'd say Zynq is a far more complex bitstream than just a vanilla FPGA. Zynq's PL is a Xilinx 7 Series fabric, I wouldn't say both are much different in complexity. I'm not saying they're simple, tough...