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If they want to keep the bitstream format closed for some deranged IP reason - ok, fine. Just document all the cells (they do it to an extend anyway) and provid
by sklogic 11y ago
If they want to keep the bitstream format closed for some deranged IP reason - ok, fine. Just document all the cells (they do it to an extend anyway) and provide a readable format for a placed and routed layout.
This way the entire toolchain can be open source, keeping only the bitstream packer closed. Lawyers are happy, users are happy - win-win.
- sobkas 11y agoBut then you could potentially change fpga supplier by only replacing bitstream packer, why would vendor allowed that?
- sklogic 11y agoCell libraries would still be incompatible. Your only possible portable layer is still RTL (with a lot of effort), exactly the same thing as with entirely closed toolchains.
- nickpsecurity 11y agoGood point. There's still a potential loss for them if that final synthesis phase creates a performance or energy usage advantage for them. I haven't seen any experiments to find out. I do know, outside of device characteristics, they mainly compete on how well their EDA tools utilize them.