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Has this guy ever written a test bench? One might not see the usefulness of interfaces (wire bundle kind) if they just do design. But they are very helpful in
by DigitalJack 11y ago
Has this guy ever written a test bench? One might not see the usefulness of interfaces (wire bundle kind) if they just do design. But they are very helpful in verification.
- krupan 11y agoThe thing is (that he didn't really take the time to explain), we could have accomplished the same thing without introducing yet another reserved word. Modules could take structs or classes as ports and you'd have the same benefit as interfaces. interfaces are redundant and introduce unnecessary complexity and confusion. In my experience designers love the idea of interfaces too. Far easier to replicate signals down through a module hierarchy if all modules can use the same interface. Designers too get frustrated that interfaces are not just modules or structs though.
- DigitalJack 11y agoBut an interface isolates timing. Assuming you use it ( I do ).
- krupan 11y agoHow so?
- DigitalJack 11y agoclock blocks
- krupan 11y agoWhich is yet another SystemVerilog feature that doesn't necessarily need to be tied to the interface language feature.