The implementations may have converged but there's still hard differences in the ISA. RISC (including ARM) has fixed-width instructions, x86 has variable width.

The implementations may have converged but there's still hard differences in the ISA. RISC (including ARM) has fixed-width instructions, x86 has variable width. RISC (including ARM again) is load-store, x86 allows memory to be sources or destinations. So ARM can have simpler decoder logic, if nothing else.