42 ms·

Maybe Clockless Chip Design's Time Has Come

throwaway000002 11y ago
Not that the article is particularly detailed, but squinting at the clock diagram for Wave Semi, it appears to be a some kind of token passing, where the token is the clock. I guess this question is for the semi- folks out there: given any n-bit boolean function, for smallish n, is there a way to implement the function so that the output is rock-stable (within reason) and only flips if given an input flip the corresponding function flips? Because, if not, I don't see how this clock passing system won't require factoring in logic delay. I'm sure a lot of details have been elided. Also, if it isn't apparent, I have no logic design knowledge. All I know, from an outsider's perspective, having a global clock is ludicrous. When will designers finally kill it?! Us software people have had to kill the concept of intrinsic clocks with our consensus protocols for a while now...
- javcasas 11y ago
  "Given any n-bit boolean function, for smallish n, is there a way to implement the function so that the output is rock-stable (within reason) and only flips if given an input flip the corresponding function flips?" Yep, there is a way. So you are designing your logic circuit as usual: 1. For each input, decide the output 2. Simplify the function using a Karnaugh Map https://en.wikipedia.org/wiki/Karnaugh_map https://en.wikipedia.org/wiki/Karnaugh_map 3. From the Karnaugh Map, implement it with AND-OR gates. When you are doing the Karnaugh Map you have to ensure every adjacent 1 or 0 (depending if you are doing standard or inverse logic) are grouped together. You will use more gates to implement the same logic. Or you can use less gates, and wait for the output to stabilize, you know, with a clock. Update: Wikipedia shows an example: https://en.wikipedia.org/wiki/File:K-map_6,8,9,10,11,12,13,14_anti-race.svg https://en.wikipedia.org/wiki/File:K-map_6,8,9,10,11,12,13,1... This has a race condition on the inverse implementation, and thus can generate glitches if used in an asynchronous circuit (but it is fine on a synchronous one): https://upload.wikimedia.org/wikipedia/commons/archive/0/02/20071022024729!K-map_6%2C8%2C9%2C10%2C11%2C12%2C13%2C14_anti-race.svg https://upload.wikimedia.org/wikipedia/commons/archive/0/02/... We can fix it adding another Karnaugh group, thus making it glitch-free, and then can be used in asynchronous circuits: https://upload.wikimedia.org/wikipedia/commons/archive/0/02/20100810221056!K-map_6%2C8%2C9%2C10%2C11%2C12%2C13%2C14_anti-race.svg https://upload.wikimedia.org/wikipedia/commons/archive/0/02/...
  - throwaway000002 11y ago
    Cool, thanks javcasas for that intro to Karnaugh maps. I haven't looked at them closely enough to fully understand how they capture "race conditions", but I'll do so on the weekend. I wonder if any specialists in combinatorial design theory have studied these objects. There could be some neat mathematics that has yet to be applied to circuit design!
    - javcasas 11y ago
      The race conditions are not really apparent on Karnaugh maps. They appear once you understand there are no single pair of logic gates in the world that are exactly equal. Every logic gate is slightly slower or faster than the others, even in the same chip. This leads to every level change to be discrete in time, and never exactly aligned with others, which leads to glitches. Silly example: Let's imagine we are implementing the logic operation A OR (NOT A), which should be 1 always. We implement it as an OR gate with two inputs. On the first input we put A through a buffer. On the second input we put A through a NOT gate. Now let's switch A from 0 to 1. One of these two sequences of events will happen: Sequence 1: 0. Nothing has happened yet. The OR gate has 0,1 on its inputs. Output=1. 1. The buffer sets its output to 1. The OR gate has 1,1 on its inputs. Output=1. 2. The NOT gate sets its output to 0. The OR gate has 1,0 on its inputs. Output=1 During all the sequence the output has been 1, so everything is fine. Sequence 2: 0. Nothing has happened yet. The OR gate has 0,1 on its inputs. Output=1. 1. The NOT gate sets its output to 0. The OR gate has 0,0 on its inputs. Output=0 2. The buffer sets its output to 1. The OR gate has 1,0 on its inputs. Output=1. Did you see it? During a split-second the output was 0, even though theoretically it should have been 1 all the time. That's your glitch. If your system is synchronous, it means it has a clock, which means the system ignores everything that happens between clock ticks. If your ticks are sufficiently large (as it should be), the glitches will happen before the next tick. So your system will "stabilize" into the right output before the next tick, and everything is fine. But if your system doesn't use a clock, these glitches will be propagated to other parts, causing trouble all over the place.
      - throwaway000002 11y ago
- eternalban 11y ago
  > Us software people .. Hardware folk have been way ahead of this curve, actually. MESI was big news in H/W cliques long (long) before it started bubbling up in pop software space around a few years ago. Also, us software people haven't really solved the problem of high performance consensus, either. (Cue in for Aphyr link.)
  - throwaway000002 11y ago
    I'm not sure if I'm mistaken, but I think the hardware guys get to have MESI because they get to assume their "network", the circuit, is infallible. You can build MESI on paxos, if you wanted. Although I think you'd be layering abstractions unnecessarily unless you have a specific use case. I'd have to think about it but perhaps there's a cache-coherent data centre scale "processor", with awful non-uniform memory access performance, sprouting random processor hotplug events, waiting to be built. Who knows? Probably somebody inside Google is working on this very thing a we speak...
    - eternalban 11y ago
      (Hardware has 'soft partitions' that manifest as pipeline stalls.) My point was merely that H/W people had to confront this issue before us.
- StringyBob 11y ago
  Modern system-on-chip designs don't really use a global clock anyway. It's more just local synchronous islands which communicate over asynchronous interfaces - i.e. https://en.wikipedia.org/wiki/Globally_asynchronous_locally_synchronous https://en.wikipedia.org/wiki/Globally_asynchronous_locally_...
brudgers 11y ago
Asynchronous circuits: https://en.wikipedia.org/wiki/Asynchronous_circuit https://en.wikipedia.org/wiki/Asynchronous_circuit
- sprash 11y ago
  If you look at rather dubious "disadvantages" like "Fewer people are trained in this style compared to synchronous design" or "Incompatible with commercial EDA tools" and the same time the vast amount of advantages this looks like a rather low hanging fruit. An asynchronous ARM64 design with potential more than 3 times better performance per watt will sell like hot cakes.
  - RachelF 11y ago
    It will only sell like hot cakes if you can get it reliable. The extra speed always tempting, but a few real builds and the real world of device variation show why the clocked designs are still used.
    - mjbs 11y ago
      Asynchronous computers are commercially available right now which have been shown to be fully reliable. Asynchronous design has been an area of research for a long time and many successful computers have been built. Why is device variation a reason against asynchronous design? If anything I'd say that is a reason for it. Clocked designs must account for the worst case variation and reduce the clock speed accordingly. An asynchronous design on the other hand will run as fast as physically possible.
      - javcasas 11y ago
        If I understand it properly, asynchronous circuits also work at the slowest speed required, thus minimizing power usage. They are really fast when there is something to do, and they stop completely when there is nothing to do. Thus the "sleep mode" should be ludicrously low power, just the leakage current of the transistors: some nA for each gate.
AYBABTME 11y ago
I wonder how real time systems would work without a clock to synchronize everything.
- wmf 11y ago
  You can always incorporate some synchronous logic where it makes sense, like measuring time.
- davelnewton 11y ago
  It's not that there aren't clock signals available, and real-time systems are almost always better described as "deterministic".
- javcasas 11y ago
  Not everything has to be asynchronous. For example, if your real-time system has to respond in less than 1ms, all you have to do is design a system able to respond in less than 1ms. If your system has to respond in exactly 1ms, you take the previous system (the one able to respond in less than 1ms) and use a 1ms clock/timer/monostable to delay it.
- nraynaud 11y ago
  actually you would want your system to react at the speed of its input (the world as seen form its point of view), not at the speed of its clock. And if you actually wanted a clock (say for an alarm clock in the morning), you could still input a clock to your system, that wouldn't entitle gating the whole system and having clock domains and that stuff.
  - davelnewton 11y ago
    That's not necessarily true, especially when interfacing with mechanical components.
softbuilder 11y ago
See also, FLEET[1]. I'm surprised this hasn't gained more traction(or at least hype). I saw Sutherland give a talk about it in 2011/2012 or so. [1]https://inst.eecs.berkeley.edu/~cs152/fa06/lecnotes/async.pdf https://inst.eecs.berkeley.edu/~cs152/fa06/lecnotes/async.pd...
exabrial 11y ago
Didn't some company have a clockless ARM core available a few years back?
- davelnewton 11y ago
  Yes, about ten years ago: http://www.eetimes.com/document.asp?doc_id=1299083 http://www.eetimes.com/document.asp?doc_id=1299083 There were chips before that, too.
- ropiku 11y ago
  Manchester University did develop an asynchronous ARM compatible chip: http://apt.cs.manchester.ac.uk/projects/processors/amulet/ http://apt.cs.manchester.ac.uk/projects/processors/amulet/
DigitalJack 11y ago
I remember this company from about 10 years ago. I don't remember the company name, but the logic was called Null Control Logic then.
- nickpsecurity 11y ago
  Theseus Research. They're in my other comment in this thread with other links.
andmarios 11y ago
This field has a well established name: asynchronous logic/circuit. The author of the article failed to even mention once this term, instead repeating the term “clockless” as he was in some kind of branding spree. Furthermore one of the article's tags was “apple”, despite AFAIK the content not being affiliated with apple in any way.
- drewm1980 11y ago
  Apple's in there as part of the dev history, though it just sounds like they hired up some of the engineers working on this to work on other projects.
parma 11y ago
Another very interesting async design is GreenArrays GA144: "This very powerful and versatile chip consists of an 18x8 array of architecturally identical, independent, complete F18A computers, or nodes, each of which operates asynchronously. Each computer is capable of performing a basic ALU instruction in ~1.5 nanoseconds for an energy cost on the order of 7 picojoules". Programmed in Forth. http://www.greenarraychips.com/index.html http://www.greenarraychips.com/index.html
- ant6n 11y ago
  That would be 667 MHz at 4.7 milliwatts for people who believe in different units.
  - i336_ 11y ago
    That is impressive power consumption. I'll admit I'm not especially familiar with the field, but that sounds quite exceptional to me. Is there anything out there offering this sort of price/performance ratio that's easily accessible, ideally programmable using open-source hobbyist tools?
nraynaud 11y ago
I think there is a technological path for gradually introducing synchronous design in clocked world: you can give them clocked inputs without problem, and you can gate their output at their worst propagation time without problem either. I think with such an easy technological path, there is no intrinsic reason not to have them around us, even exposed as clocked systems. If someone told me today that there already are synchronous blocks in a famous silicon chip I would certainly not be surprised. For example, I'm not a silicon guy so I'm guessing, but adders are generally exposed as one cycle instructions in software, but they still have to propagate the carry on the width of the word, so I guess adders are simply a tree of gate that synchronously propagate and we know the carry propagates faster than the clock tick.
- rdc12 11y ago
  That sounds like you are hinting at some form of prefix-adder, they are quite need in that they scale (N being the bit length), in a logarithmic way.
theon144 11y ago
>They also had to invent a new type of gate – one that switches based on the sum of the number of its input that are at logic 1. What? Isn't that just AND? I wasn't really too clever from looking at the diagram provided, so I might be missing something.
- akovaski 11y ago
  Looking at the waveform graph on the site, it looks like it turns the output to 1 when both inputs are 1, and turns the output to 0 when both inputs are 0 (In other words, it assigns the output to the inputs when the inputs are in agreement). Though, that's just a guess.
ertyuiopas 11y ago
Leakage is the big problem in deep submicron. You can't keep a state without periodically refreshing it (cf. DRAM). Also, asynchronous circuits are very prone to metastability. If these problems were easily solved, we'd have seen this old idea be widespread by now.
BooneJS 11y ago
Fulcrum Microsystems was a Clockless ASIC startup that was acquired by Intel in 2011 for their Ethernet switch silicon technology. http://newsroom.intel.com/community/intel_newsroom/blog/2011/07/19/intel-to-acquire-fulcrum-microsystems http://newsroom.intel.com/community/intel_newsroom/blog/2011...
nickpsecurity 11y ago
I recently dropped a lot of links to asynchronous cell libraries, chips, and so on in this comment: https://news.ycombinator.com/item?id=10621937 https://news.ycombinator.com/item?id=10621937 Just in case pro's want to comment on any of it or think it's cool.
n00b101 11y ago
I recently asked an Intel chip designer if asynchronous circuits could be a way to deal with stalling of Moore's Law and he was adamant that asynchronous circuits are a "fantasy." His argument was that even though synchronous use about 20% of the energy on a modern, chips, with asynchronous you still need to pass around synchronization tokens which would double the energy required and worse it would be on the critical path.

Not that the article is particularly detailed, but squinting at the clock diagram for Wave Semi, it appears to be a some kind of token passing, where the token is the clock. I guess this question is for the semi- folks out there: given any n-bit boolean function, for smallish n, is there a way to implement the function so that the output is rock-stable (within reason) and only flips if given an input flip the corresponding function flips? Because, if not, I don't see how this clock passing system won't require factoring in logic delay. I'm sure a lot of details have been elided. Also, if it isn't apparent, I have no logic design knowledge. All I know, from an outsider's perspective, having a global clock is ludicrous. When will designers finally kill it?! Us software people have had to kill the concept of intrinsic clocks with our consensus protocols for a while now...

javcasas 11y ago
"Given any n-bit boolean function, for smallish n, is there a way to implement the function so that the output is rock-stable (within reason) and only flips if given an input flip the corresponding function flips?" Yep, there is a way. So you are designing your logic circuit as usual: 1. For each input, decide the output 2. Simplify the function using a Karnaugh Map https://en.wikipedia.org/wiki/Karnaugh_map https://en.wikipedia.org/wiki/Karnaugh_map 3. From the Karnaugh Map, implement it with AND-OR gates. When you are doing the Karnaugh Map you have to ensure every adjacent 1 or 0 (depending if you are doing standard or inverse logic) are grouped together. You will use more gates to implement the same logic. Or you can use less gates, and wait for the output to stabilize, you know, with a clock. Update: Wikipedia shows an example: https://en.wikipedia.org/wiki/File:K-map_6,8,9,10,11,12,13,14_anti-race.svg https://en.wikipedia.org/wiki/File:K-map_6,8,9,10,11,12,13,1... This has a race condition on the inverse implementation, and thus can generate glitches if used in an asynchronous circuit (but it is fine on a synchronous one): https://upload.wikimedia.org/wikipedia/commons/archive/0/02/20071022024729!K-map_6%2C8%2C9%2C10%2C11%2C12%2C13%2C14_anti-race.svg https://upload.wikimedia.org/wikipedia/commons/archive/0/02/... We can fix it adding another Karnaugh group, thus making it glitch-free, and then can be used in asynchronous circuits: https://upload.wikimedia.org/wikipedia/commons/archive/0/02/20100810221056!K-map_6%2C8%2C9%2C10%2C11%2C12%2C13%2C14_anti-race.svg https://upload.wikimedia.org/wikipedia/commons/archive/0/02/...
- throwaway000002 11y ago
  Cool, thanks javcasas for that intro to Karnaugh maps. I haven't looked at them closely enough to fully understand how they capture "race conditions", but I'll do so on the weekend. I wonder if any specialists in combinatorial design theory have studied these objects. There could be some neat mathematics that has yet to be applied to circuit design!
  - javcasas 11y ago
    The race conditions are not really apparent on Karnaugh maps. They appear once you understand there are no single pair of logic gates in the world that are exactly equal. Every logic gate is slightly slower or faster than the others, even in the same chip. This leads to every level change to be discrete in time, and never exactly aligned with others, which leads to glitches. Silly example: Let's imagine we are implementing the logic operation A OR (NOT A), which should be 1 always. We implement it as an OR gate with two inputs. On the first input we put A through a buffer. On the second input we put A through a NOT gate. Now let's switch A from 0 to 1. One of these two sequences of events will happen: Sequence 1: 0. Nothing has happened yet. The OR gate has 0,1 on its inputs. Output=1. 1. The buffer sets its output to 1. The OR gate has 1,1 on its inputs. Output=1. 2. The NOT gate sets its output to 0. The OR gate has 1,0 on its inputs. Output=1 During all the sequence the output has been 1, so everything is fine. Sequence 2: 0. Nothing has happened yet. The OR gate has 0,1 on its inputs. Output=1. 1. The NOT gate sets its output to 0. The OR gate has 0,0 on its inputs. Output=0 2. The buffer sets its output to 1. The OR gate has 1,0 on its inputs. Output=1. Did you see it? During a split-second the output was 0, even though theoretically it should have been 1 all the time. That's your glitch. If your system is synchronous, it means it has a clock, which means the system ignores everything that happens between clock ticks. If your ticks are sufficiently large (as it should be), the glitches will happen before the next tick. So your system will "stabilize" into the right output before the next tick, and everything is fine. But if your system doesn't use a clock, these glitches will be propagated to other parts, causing trouble all over the place.
    - throwaway000002 11y ago
eternalban 11y ago
> Us software people .. Hardware folk have been way ahead of this curve, actually. MESI was big news in H/W cliques long (long) before it started bubbling up in pop software space around a few years ago. Also, us software people haven't really solved the problem of high performance consensus, either. (Cue in for Aphyr link.)
- throwaway000002 11y ago
  I'm not sure if I'm mistaken, but I think the hardware guys get to have MESI because they get to assume their "network", the circuit, is infallible. You can build MESI on paxos, if you wanted. Although I think you'd be layering abstractions unnecessarily unless you have a specific use case. I'd have to think about it but perhaps there's a cache-coherent data centre scale "processor", with awful non-uniform memory access performance, sprouting random processor hotplug events, waiting to be built. Who knows? Probably somebody inside Google is working on this very thing a we speak...
  - eternalban 11y ago
    (Hardware has 'soft partitions' that manifest as pipeline stalls.) My point was merely that H/W people had to confront this issue before us.
StringyBob 11y ago
Modern system-on-chip designs don't really use a global clock anyway. It's more just local synchronous islands which communicate over asynchronous interfaces - i.e. https://en.wikipedia.org/wiki/Globally_asynchronous_locally_synchronous https://en.wikipedia.org/wiki/Globally_asynchronous_locally_...

brudgers 11y ago

Asynchronous circuits: https://en.wikipedia.org/wiki/Asynchronous_circuit https://en.wikipedia.org/wiki/Asynchronous_circuit

sprash 11y ago
If you look at rather dubious "disadvantages" like "Fewer people are trained in this style compared to synchronous design" or "Incompatible with commercial EDA tools" and the same time the vast amount of advantages this looks like a rather low hanging fruit. An asynchronous ARM64 design with potential more than 3 times better performance per watt will sell like hot cakes.
- RachelF 11y ago
  It will only sell like hot cakes if you can get it reliable. The extra speed always tempting, but a few real builds and the real world of device variation show why the clocked designs are still used.
  - mjbs 11y ago
    Asynchronous computers are commercially available right now which have been shown to be fully reliable. Asynchronous design has been an area of research for a long time and many successful computers have been built. Why is device variation a reason against asynchronous design? If anything I'd say that is a reason for it. Clocked designs must account for the worst case variation and reduce the clock speed accordingly. An asynchronous design on the other hand will run as fast as physically possible.
    - javcasas 11y ago
      If I understand it properly, asynchronous circuits also work at the slowest speed required, thus minimizing power usage. They are really fast when there is something to do, and they stop completely when there is nothing to do. Thus the "sleep mode" should be ludicrously low power, just the leakage current of the transistors: some nA for each gate.

AYBABTME 11y ago

I wonder how real time systems would work without a clock to synchronize everything.

wmf 11y ago
You can always incorporate some synchronous logic where it makes sense, like measuring time.
davelnewton 11y ago
It's not that there aren't clock signals available, and real-time systems are almost always better described as "deterministic".
javcasas 11y ago
Not everything has to be asynchronous. For example, if your real-time system has to respond in less than 1ms, all you have to do is design a system able to respond in less than 1ms. If your system has to respond in exactly 1ms, you take the previous system (the one able to respond in less than 1ms) and use a 1ms clock/timer/monostable to delay it.
nraynaud 11y ago
actually you would want your system to react at the speed of its input (the world as seen form its point of view), not at the speed of its clock. And if you actually wanted a clock (say for an alarm clock in the morning), you could still input a clock to your system, that wouldn't entitle gating the whole system and having clock domains and that stuff.
- davelnewton 11y ago
  That's not necessarily true, especially when interfacing with mechanical components.

softbuilder 11y ago

See also, FLEET[1]. I'm surprised this hasn't gained more traction(or at least hype). I saw Sutherland give a talk about it in 2011/2012 or so. [1]https://inst.eecs.berkeley.edu/~cs152/fa06/lecnotes/async.pdf https://inst.eecs.berkeley.edu/~cs152/fa06/lecnotes/async.pd...

exabrial 11y ago

Didn't some company have a clockless ARM core available a few years back?

davelnewton 11y ago
Yes, about ten years ago: http://www.eetimes.com/document.asp?doc_id=1299083 http://www.eetimes.com/document.asp?doc_id=1299083 There were chips before that, too.
ropiku 11y ago
Manchester University did develop an asynchronous ARM compatible chip: http://apt.cs.manchester.ac.uk/projects/processors/amulet/ http://apt.cs.manchester.ac.uk/projects/processors/amulet/

DigitalJack 11y ago

I remember this company from about 10 years ago. I don't remember the company name, but the logic was called Null Control Logic then.

nickpsecurity 11y ago
Theseus Research. They're in my other comment in this thread with other links.

andmarios 11y ago

This field has a well established name: asynchronous logic/circuit. The author of the article failed to even mention once this term, instead repeating the term “clockless” as he was in some kind of branding spree. Furthermore one of the article's tags was “apple”, despite AFAIK the content not being affiliated with apple in any way.

drewm1980 11y ago
Apple's in there as part of the dev history, though it just sounds like they hired up some of the engineers working on this to work on other projects.

parma 11y ago

Another very interesting async design is GreenArrays GA144: "This very powerful and versatile chip consists of an 18x8 array of architecturally identical, independent, complete F18A computers, or nodes, each of which operates asynchronously. Each computer is capable of performing a basic ALU instruction in ~1.5 nanoseconds for an energy cost on the order of 7 picojoules". Programmed in Forth. http://www.greenarraychips.com/index.html http://www.greenarraychips.com/index.html

ant6n 11y ago
That would be 667 MHz at 4.7 milliwatts for people who believe in different units.
- i336_ 11y ago
  That is impressive power consumption. I'll admit I'm not especially familiar with the field, but that sounds quite exceptional to me. Is there anything out there offering this sort of price/performance ratio that's easily accessible, ideally programmable using open-source hobbyist tools?

nraynaud 11y ago

I think there is a technological path for gradually introducing synchronous design in clocked world: you can give them clocked inputs without problem, and you can gate their output at their worst propagation time without problem either. I think with such an easy technological path, there is no intrinsic reason not to have them around us, even exposed as clocked systems. If someone told me today that there already are synchronous blocks in a famous silicon chip I would certainly not be surprised. For example, I'm not a silicon guy so I'm guessing, but adders are generally exposed as one cycle instructions in software, but they still have to propagate the carry on the width of the word, so I guess adders are simply a tree of gate that synchronously propagate and we know the carry propagates faster than the clock tick.

rdc12 11y ago
That sounds like you are hinting at some form of prefix-adder, they are quite need in that they scale (N being the bit length), in a logarithmic way.

theon144 11y ago

>They also had to invent a new type of gate – one that switches based on the sum of the number of its input that are at logic 1. What? Isn't that just AND? I wasn't really too clever from looking at the diagram provided, so I might be missing something.

akovaski 11y ago
Looking at the waveform graph on the site, it looks like it turns the output to 1 when both inputs are 1, and turns the output to 0 when both inputs are 0 (In other words, it assigns the output to the inputs when the inputs are in agreement). Though, that's just a guess.

ertyuiopas 11y ago

Leakage is the big problem in deep submicron. You can't keep a state without periodically refreshing it (cf. DRAM). Also, asynchronous circuits are very prone to metastability. If these problems were easily solved, we'd have seen this old idea be widespread by now.

BooneJS 11y ago

Fulcrum Microsystems was a Clockless ASIC startup that was acquired by Intel in 2011 for their Ethernet switch silicon technology. http://newsroom.intel.com/community/intel_newsroom/blog/2011/07/19/intel-to-acquire-fulcrum-microsystems http://newsroom.intel.com/community/intel_newsroom/blog/2011...

nickpsecurity 11y ago

I recently dropped a lot of links to asynchronous cell libraries, chips, and so on in this comment: https://news.ycombinator.com/item?id=10621937 https://news.ycombinator.com/item?id=10621937 Just in case pro's want to comment on any of it or think it's cool.

n00b101 11y ago

I recently asked an Intel chip designer if asynchronous circuits could be a way to deal with stalling of Moore's Law and he was adamant that asynchronous circuits are a "fantasy." His argument was that even though synchronous use about 20% of the energy on a modern, chips, with asynchronous you still need to pass around synchronization tokens which would double the energy required and worse it would be on the critical path.