I was wondering how radically this architecture differs from more conventional x86 cores, and found this: "An Overview of Programming for Intel Xeon processors

I was wondering how radically this architecture differs from more conventional x86 cores, and found this: "An Overview of Programming for Intel Xeon processors and Intel Xeon Phi coprocessors (2012)" [0]. This paper refers to a slightly older architecture - "Knight's Corner", but it should be roughly the same. Essentially, it has a large number of x86 cores with 4 in-order threads per core. Each core has a 512 KB L2 cache and the entire coprocessor is cache-coherent through a high-speed ring bus. There is also some quantity of GDDR5 (up to 8GB) on said ring bus. The great advantage over Xeon is its scaling to very high levels of parallelism: though threads on the same core will benefit from data locality, the architecture scales uniformly with more cores unlike a NUMA multi-socket setup. There's more information about the sorts of optimisations required to get good performance in the paper, but they're much the same sort of things as for Xeon. Also, according to the paper, any algorithm well suited for a GPU is well suited to the Phi architecture, though the Phi architecture is far more general-purpose in its applications. [0] - https://software.intel.com/sites/default/files/article/330164/an-overview-of-programming-for-intel-xeon-processors-and-intel-xeon-phi-coprocessors_1.pdf https://software.intel.com/sites/default/files/article/33016...