4 ms·
I would guess even less than 24. Today you can write your structural Verilog implementation, run an automatic mapping to a PDK standard cell library, and simula
by craigjb 11y ago
I would guess even less than 24. Today you can write your structural Verilog implementation, run an automatic mapping to a PDK standard cell library, and simulate to verify. The hardest part might be floor planning for something like that today. The placement and routing can all be automagical, and you won't have any timing closure issues at these speeds. I'd guess a single student could do it if sufficiently motivated. And, with CMP or MOSIS you could have it manufactured on a 350nm CMOS process by AMS for $2200 (20-25 pcs).
- Gracana 11y agoIs it really that cheap? I was just looking into this a little and I thought it was more like $10-20k for a dozen large-ish CMOS process. Got a link to pricing details for stuff in the ballpark you gave?
- andmarios 11y ago24 people for doing the work Intel's engineers did. That is given the ISA and some hints (e.g a list of components they are going to need), to start from basic components and boolean expressions, convert them to CMOS circuits by hand and then draw them efficiently in a software like Magic.