3 ms·
Zynq from Xilinx uses an AXI bus between the CPU and logic. The first gen ones are not cache coherent between the logic and CPU but I believe UltraScale will be
by planteen 11y ago
Zynq from Xilinx uses an AXI bus between the CPU and logic. The first gen ones are not cache coherent between the logic and CPU but I believe UltraScale will be. I don't know much about PCIe, but how is AXI much lower latency?
- reisgabrieljoao 11y agoThere is a cache coherent FPGA-CPU DMA interface in Zynq-7000: the Accelerator Coherency Port (ACP).