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Yes, it is an unfortunate catch-22. I think the secret is that, due to their simplicity and analyzability, it's possible to make extraordinarily powerful DSLs

Yes, it is an unfortunate catch-22. I think the secret is that, due to their simplicity and analyzability, it's possible to make extraordinarily powerful DSLs that can truly excel at their tasks in a way that general-purpose languages can not. SQL is a perfect example of this. The fact that it is (barring recursive CTEs) not Turing-complete is what permits very intelligent automatic query optimization. I can write simple, clear, concise, performant SQL code that blows the pants off anything I can do without extraordinary effort in a general-purpose language. It is this that has made SQL so indispensable and enduring a tool.

nickpsecurity 11y ago
Or you can get both with a powerful general purpose language subject to easy analysis and supporting DSL's. What I can do with that will blow the pants off your SQL. Matter of fact, I can start with a DSL for clarity/automation, manually optimize it if I choose in same language, and (if Scheme) compile that all the way down to logic gates. That's power right there.
- colanderman 11y ago
  I'm not really sure the point of your post. Why should I roll my own relational query engine in Scheme when I can use one with hundreds of man-years of development, and thousands of man-years of testing behind it, like PostgreSQL? Also, I sincerely hope you're not trying to synthesize ASICs out of code from a language with constructs like call/cc.
  - fabulist 11y ago
    > Also, I sincerely hope you're not trying to synthesize ASICs out of code from a language with constructs like call/cc. Many EEs prefer to use functional languages. If you're wondering why, spend some quality time with Verilog and VHDL. Edit: Though after looking up call/cc, my guess is that hardware compilers don't support it.
    - GFK_of_xmaspast 11y ago
      My experience with EEs it that their preferred language is almost uniformly matlab.
      - nickpsecurity 11y ago
        They have a great hardware synthesis tool now that costs low, five digits. Just for math-style algorithms rather than arbitrary programs. Prototype algorithm is Matlab language, then deploy to HDL with plugin.
    - colanderman 11y ago
      I am an EE. I have designed fully-synthesized ASICs in Verilog for money. If you ignore the simulation constructs of Verilog (which you should, if you're designing something to be synthesizable), Verilog is a purely declarative reactive language, and a damn good one at that. (Verilog, BTW, has stratified programming-in-the-large constructs.) You can't synthesize "functional programs"; there's no analogue of recursion in hardware. You can only synthesize things that happen to look like functional programs because they're written using sexprs and macros and expand out to a static circuit graph which is exactly what Verilog is.
      - fabulist 11y ago
        I guess it would be more accurate to say, when I was trying to learn Verilog, people I knew tried to convince me to abandon Verilog in favor of Haskell flavors. This gave me the (perhaps false) impression that this was common practice.
        tel 11y ago
        The Haskell flavored tend to be clever ways to get a functional language without recursion.
        nickpsecurity 11y ago
        It's not common but many swear by it in form of Bluespec: a Haskell extension/modification for HDL with RTL output. Look them up. Further, dig in the CHERI project for their processor source as it's Bluespec for a security-enhanced, MIPS64 processor which might give you a good idea about what the language is like. Very real-world project. Already runs capability-secure FreeBSD. Most newcomers' Verilog projects are less complicated. :) https://www.cl.cam.ac.uk/research/security/ctsrd/beri/ https://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Also you might find Synflow's HDL interesting. It's on my backlog as I'd rather get diverse and experienced HDL users to put it through the paces. They have several, non-trivial IP for sale that they coded in it and for cheap, too. http://cx-lang.org/ http://cx-lang.org/

nickpsecurity 11y ago

Or you can get both with a powerful general purpose language subject to easy analysis and supporting DSL's. What I can do with that will blow the pants off your SQL. Matter of fact, I can start with a DSL for clarity/automation, manually optimize it if I choose in same language, and (if Scheme) compile that all the way down to logic gates. That's power right there.

colanderman 11y ago
I'm not really sure the point of your post. Why should I roll my own relational query engine in Scheme when I can use one with hundreds of man-years of development, and thousands of man-years of testing behind it, like PostgreSQL? Also, I sincerely hope you're not trying to synthesize ASICs out of code from a language with constructs like call/cc.
- fabulist 11y ago
  > Also, I sincerely hope you're not trying to synthesize ASICs out of code from a language with constructs like call/cc. Many EEs prefer to use functional languages. If you're wondering why, spend some quality time with Verilog and VHDL. Edit: Though after looking up call/cc, my guess is that hardware compilers don't support it.
  - GFK_of_xmaspast 11y ago
    My experience with EEs it that their preferred language is almost uniformly matlab.
    - nickpsecurity 11y ago
      They have a great hardware synthesis tool now that costs low, five digits. Just for math-style algorithms rather than arbitrary programs. Prototype algorithm is Matlab language, then deploy to HDL with plugin.
  - colanderman 11y ago
    I am an EE. I have designed fully-synthesized ASICs in Verilog for money. If you ignore the simulation constructs of Verilog (which you should, if you're designing something to be synthesizable), Verilog is a purely declarative reactive language, and a damn good one at that. (Verilog, BTW, has stratified programming-in-the-large constructs.) You can't synthesize "functional programs"; there's no analogue of recursion in hardware. You can only synthesize things that happen to look like functional programs because they're written using sexprs and macros and expand out to a static circuit graph which is exactly what Verilog is.
    - fabulist 11y ago
      I guess it would be more accurate to say, when I was trying to learn Verilog, people I knew tried to convince me to abandon Verilog in favor of Haskell flavors. This gave me the (perhaps false) impression that this was common practice.
      - tel 11y ago
        The Haskell flavored tend to be clever ways to get a functional language without recursion.
      - nickpsecurity 11y ago
        It's not common but many swear by it in form of Bluespec: a Haskell extension/modification for HDL with RTL output. Look them up. Further, dig in the CHERI project for their processor source as it's Bluespec for a security-enhanced, MIPS64 processor which might give you a good idea about what the language is like. Very real-world project. Already runs capability-secure FreeBSD. Most newcomers' Verilog projects are less complicated. :) https://www.cl.cam.ac.uk/research/security/ctsrd/beri/ https://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Also you might find Synflow's HDL interesting. It's on my backlog as I'd rather get diverse and experienced HDL users to put it through the paces. They have several, non-trivial IP for sale that they coded in it and for cheap, too. http://cx-lang.org/ http://cx-lang.org/