You might want to read up on HMC; this enables 10X the DRAM bandwidth to the FPGA. Since DRAM bandwidth is a bottleneck for many real applications, this is a b

You might want to read up on HMC; this enables 10X the DRAM bandwidth to the FPGA. Since DRAM bandwidth is a bottleneck for many real applications, this is a big deal. That said, the PR contains nothing about capacity, latency, nor price, so it's near-pointless.