3 ms·

Actually, you can align on any byte in x86 and it will still work, the accessing is just slower (And you loose some other guarantees). That said, lots of malloc

by DSMan195276 11y ago

Actually, you can align on any byte in x86 and it will still work, the accessing is just slower (And you loose some other guarantees). That said, lots of malloc implementations on 32-bit x86 actually return 8-byte aligned addresses, for the reason that you can have 64-bit ints and such which benefit from 8-byte alignment.

nkurz 11y ago
the accessing is just slower While there are some cases where this is an issue (writes that cross 4KB page boundaries), this generally isn't true for any x86/x64 processor made in the last decade. There may be legitimate portability reasons for avoiding unaligned access, but performance on x86 is probably not a good reason.
- DSMan195276 11y ago
  I generally agree with what you've said, but a performance penalty is definitely still possible by crossing a cache-line boundary - I would assume unaligned accesses are just as fast as aligned ones only when the value itself is still contained within the same cache-line. But with that said, I think you're right in that the performance here isn't really the big deal - the portability reasons alone are enough to justify making sure the returned pointer is correctly aligned.
- asveikau 11y ago
  AFAIK atomic reads, writes, and read-modify-write instructions still need alignment on x86.
  - nkurz 11y ago
    Good point, although the requirement is just that they do not cross a 64B cacheline: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf http://www.intel.com/content/dam/www/public/us/en/documents/... 8.1.1 Guaranteed Atomic Operations The P6 family processors (and newer processors since) guarantee that the following additional memory operation will always be carried out atomically: • Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line The first P6 was Pentium Pro, which came out in 1995. It does go on to say that although modern processors will guarantee atomic operations that cross cache lines, it's a bad practice that can badly hurt performance.

nkurz 11y ago

the accessing is just slower While there are some cases where this is an issue (writes that cross 4KB page boundaries), this generally isn't true for any x86/x64 processor made in the last decade. There may be legitimate portability reasons for avoiding unaligned access, but performance on x86 is probably not a good reason.

DSMan195276 11y ago
I generally agree with what you've said, but a performance penalty is definitely still possible by crossing a cache-line boundary - I would assume unaligned accesses are just as fast as aligned ones only when the value itself is still contained within the same cache-line. But with that said, I think you're right in that the performance here isn't really the big deal - the portability reasons alone are enough to justify making sure the returned pointer is correctly aligned.
asveikau 11y ago
AFAIK atomic reads, writes, and read-modify-write instructions still need alignment on x86.
- nkurz 11y ago
  Good point, although the requirement is just that they do not cross a 64B cacheline: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf http://www.intel.com/content/dam/www/public/us/en/documents/... 8.1.1 Guaranteed Atomic Operations The P6 family processors (and newer processors since) guarantee that the following additional memory operation will always be carried out atomically: • Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line The first P6 was Pentium Pro, which came out in 1995. It does go on to say that although modern processors will guarantee atomic operations that cross cache lines, it's a bad practice that can badly hurt performance.