3 ms·
>At the high-end, the power-costs of ISA are negligible. Even at laptop levels of power consumption it's barely noticeable. Once an Intel chip has decoded the i
by scythe 11y ago
>At the high-end, the power-costs of ISA are negligible. Even at laptop levels of power consumption it's barely noticeable. Once an Intel chip has decoded the instructions to uOps, it is mostly on an even playing-field with RISC chips.
This doesn't actually answer my question at all, it's just a canned response to something I alluded to in my question (CISC vs. RISC) and a debate which I don't fully understand and would rather avoid. The question was why does POWER consume so much power, not why doesn't POWER being RISC matter? The only reason I compared it to MIPS and ARM was that I thought it was similar to those architectures and they're considered to be low-power.
The impetus is that POWER is actually worse than other architectures, including x86, for unexplained reasons, w.r.t. power consumption.
- aidenn0 11y agoPOWER consumes more power because IBM has not optimized for that to the degree that Intel has. The PA6T was extremely power efficient (and was designed by a team headed by the same person who designed StrongARM (became X-scale) and SiByte's (now purchaesed by Broadcom) MIPS chips). [edit] To clarify, the difference between ISAs for power efficiency is negligible at all but the lowest powers, which is what I was trying to say in my original response. The Pentium 4 was far less power efficient than the contemporary G4 PowerPC, as a counterexample. If the power difference between two chips is more than 1 watt per instruction decode unit, you can probably safely assume it's not due to the ISA.