Thinking about it again, from my calculation below, if those packets are coming from RAM then you are bound to, say, 25GB/s incoming, 25GB/s outgoing. Since H

Thinking about it again, from my calculation below, if those packets are coming from RAM then you are bound to, say, 25GB/s incoming, 25GB/s outgoing. Since Haswell L1 cache seems to allow a peak bandwidth of 64 byte loads + 32 byte store per cycle, so this would match the CPU throughput and then this suggests, if the lifecycle is "bring from ram" "copy in and out of L1 cache", "put back in RAM", then those copies may well be free given you are choking on RAM to begin with.