3 ms·
Why do you care about efficiency? Use all your block rams for a cache to mitigate the dram inefficiency, and use the simplest possible controller. They can be q
by sklogic 11y ago
Why do you care about efficiency? Use all your block rams for a cache to mitigate the dram inefficiency, and use the simplest possible controller. They can be quite simple, really, see this one for example: https://github.com/fpga-logi/logi-hard/blob/master/hdl/interface/SDRAM_Controller.vhd https://github.com/fpga-logi/logi-hard/blob/master/hdl/inter...
- pdw 11y agoThat's still more than twice as long as the current largest module, and now you need to add caches to the system. (To be clear, I'm not involved in Oberon's design, I'm just explaining the reasoning as I understand it.)