3 ms·

By using the open source toolchains, of course. See http://opencircuitdesign.com/qflow/ http://opencircuitdesign.com/qflow/ - it's capable of producing the OSU

by sklogic 11y ago

By using the open source toolchains, of course. See http://opencircuitdesign.com/qflow/ http://opencircuitdesign.com/qflow/ - it's capable of producing the OSU 0.35um output, ready for a fab. And with such a node you can inspect the result with nearly a bare eye.

nickpsecurity 11y ago
I've been wanting to know what they've actually fabbed rather than merely synthesized. What link do you have on them doing an ASIC-proven design at 0.35um? Not just in theory but actually doing it and the chip worked. Far as getting OSS flows lower, I've been collecting methods for doing that. Physical [re-]synthesis is the next step for 130nm and 90nm. A few other tricks they use. I've collected a few papers on methods of doing as many as possible so academics can reimplement them for Yosys, Odin, ABC, etc in the future. It's critical that we get open flows for 90nm. We can do 180nm first as it's still highly useful, esp for custom. However, 90nm is better for standard cell and flash memory. My mindset is that we can combine proprietary tools and open tools in a hybrid approach. Let the proprietary tools catch all the errors, guide re-synthesis, etc. So long as they can be made to produce a series of traces for synthesis and test vectors that open-source tools can check. One or more EDA vendors might go for this as it keeps their secrets secret and profits high while letting us do much easier work that OSS tools are already close to handling. I mean, we still strive for open EDA in long term but use this for interim. What you think?
- sklogic 11y ago
  Quoting the qflow site: > Early versions of the qflow digital flow were used to create digital circuits used in high-performance commercial integrated circuits. It's real, and it works! So, likely, the OSU cell library was really used for commercial fabrication ( http://vlsiarch.ecen.okstate.edu/flow/# http://vlsiarch.ecen.okstate.edu/flow/# ). I think you're right, OSS can coexist with the proprietary cell libraries and P&R tools. I am (optimistically) expecting that in the near future we'll witness a revolution in vlsi similar to what happened to the PCB fabrication - with the fabs becoming accessible to small companies and even hobbyists. And this should kick start an improvement in both the OSS tools ecosystem and the current closed, secretive world of Cadence, Synopsys and alike.
  - nickpsecurity 11y ago
    Oh ok. Come to think of it, I could just contact Cliff and ask him what the successes/limits are. I'm sure he'd be more than helpful haha. re the revolution Oh, then I'm sure Mentor Graphics' latest move might surprise and excite you: https://www.systemvision.com/ https://www.systemvision.com/

by sklogic 11y ago

nickpsecurity 11y ago

I've been wanting to know what they've actually fabbed rather than merely synthesized. What link do you have on them doing an ASIC-proven design at 0.35um? Not just in theory but actually doing it and the chip worked. Far as getting OSS flows lower, I've been collecting methods for doing that. Physical [re-]synthesis is the next step for 130nm and 90nm. A few other tricks they use. I've collected a few papers on methods of doing as many as possible so academics can reimplement them for Yosys, Odin, ABC, etc in the future. It's critical that we get open flows for 90nm. We can do 180nm first as it's still highly useful, esp for custom. However, 90nm is better for standard cell and flash memory. My mindset is that we can combine proprietary tools and open tools in a hybrid approach. Let the proprietary tools catch all the errors, guide re-synthesis, etc. So long as they can be made to produce a series of traces for synthesis and test vectors that open-source tools can check. One or more EDA vendors might go for this as it keeps their secrets secret and profits high while letting us do much easier work that OSS tools are already close to handling. I mean, we still strive for open EDA in long term but use this for interim. What you think?

sklogic 11y ago
Quoting the qflow site: > Early versions of the qflow digital flow were used to create digital circuits used in high-performance commercial integrated circuits. It's real, and it works! So, likely, the OSU cell library was really used for commercial fabrication ( http://vlsiarch.ecen.okstate.edu/flow/# http://vlsiarch.ecen.okstate.edu/flow/# ). I think you're right, OSS can coexist with the proprietary cell libraries and P&R tools. I am (optimistically) expecting that in the near future we'll witness a revolution in vlsi similar to what happened to the PCB fabrication - with the fabs becoming accessible to small companies and even hobbyists. And this should kick start an improvement in both the OSS tools ecosystem and the current closed, secretive world of Cadence, Synopsys and alike.
- nickpsecurity 11y ago
  Oh ok. Come to think of it, I could just contact Cliff and ask him what the successes/limits are. I'm sure he'd be more than helpful haha. re the revolution Oh, then I'm sure Mentor Graphics' latest move might surprise and excite you: https://www.systemvision.com/ https://www.systemvision.com/