3 ms·
memory ordering can get complicated. Here's further discussion from intel's software developer manual: section 8.2: http://www.intel.com/content/dam/www/publi
by halayli 11y ago
memory ordering can get complicated. Here's further discussion from intel's software developer manual:
section 8.2:
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf http://www.intel.com/content/dam/www/public/us/en/documents/...
- renox 11y agoCache management is also quite complicated, I was really surprised to read: https://www.reddit.com/r/programming/comments/3p9idq/false_sharing_curiosities/ https://www.reddit.com/r/programming/comments/3p9idq/false_s... http://stackoverflow.com/questions/29199779/false-sharing-and-128-byte-alignment-padding http://stackoverflow.com/questions/29199779/false-sharing-an... apparenly 'false sharing' like effect can happen with the cache line next to the one you're using.. Uh??