3 ms·
I haven't looked at the actual board design, but I'm making a few educated guesses based on people mentioning Freescale. If this is using an i.MX6, one great w
by tonyarkles 11y ago
I haven't looked at the actual board design, but I'm making a few educated guesses based on people mentioning Freescale.
If this is using an i.MX6, one great way to interface the FPGA with the CPU is through the EIM (external interface memory). It allows you a quite fast interface, without giving the FPGA direct access to RAM. It might not be fast enough to connect a 100MSPS ADC, but for many things it's quite great and easy to write both the Verilog/VHDL and the kernel-side driver for.
- nickpsecurity 11y agoThanks for the tip!
- JoachimS 11y agoThe FPGA on the Novena is connected to the EIM. The EIM is a bit of a pain to work with. Pavel (part of Cryptech core team) has done a good top level with much cleaned up constraints compared to what Bunnie provides. If anybody wants to build FPGA designs for the Novena I would recommend to start with our top level design and build setup, just clone and go. We get good performance out of the FPGA as configurable coprocessor.