The last comment is very ignorant of CPU design. Clearing the highest bits of a register is not a stupid thing to do, it's what you have to do if you don't want

The last comment is very ignorant of CPU design. Clearing the highest bits of a register is not a stupid thing to do, it's what you have to do if you don't want to have false dependencies on the previous contents of the register. Partially updating registers in an OoO system is much more expensive operation than what it seems to be for a software guy, and the naive way to use them that the comment suggested would have killed any attempts to extract workable ILP from the system. At the time, they evaluated how many registers they needed and ran simulations for 16, 32 and 64. Assuming a modern implementation with register renaming and good OoO, they found only a few % gain from 32 and practically none with 64. They decided to go with 16 to save encoding bits. If they found that x86 needed more registers, they would have added more registers, not made partial accesses more common. Remember that spilling to stack in x86 does not have a latency hit in normal conditions because all modern x86 cpus have a separate stack engine that allows the loads to retire immediately after they enter the instruction window, typically tens of cycles before any instructions immediately following them.