3 ms·
As was aptly demonstrated by x86 systems (both now and in that era), transistor budgets had grown enough by the time Cell came of age that the impact of ISAs co
by cbsmith 11y ago
As was aptly demonstrated by x86 systems (both now and in that era), transistor budgets had grown enough by the time Cell came of age that the impact of ISAs could have on overall performance was comparatively trivial. POWER had a lot of funny things about it, but it wasn't that hard to get POWER architectures to move quickly.
- protomyth 11y agoYou still have to implement the spec, and my question is about the spec. Yes, we can overcome crap which let us end up with the least liked ISA for the winner.
- cbsmith 11y agoPOWER inherited a lot of baggage from the IBM R/T, the first real go at RISC, so it was the most un-RISC-like of the RISC ISA's. That was the included all the addressing modes and a surprisingly rich ISA. Those were all considered no-no's for unlocking the advantages of RISC.
- protomyth 11y agoThanks. Is there a document / blog post that tells exactly what the baggage and addressing modes were? I've heard the problem but never found the actual specifics.
- cbsmith 11y agoWell, a fairly handy reference might be the PowerPC 601 ISA docs: http://www.freescale.com/files/32bit/doc/user_guide/MPC601UM.pdf http://www.freescale.com/files/32bit/doc/user_guide/MPC601UM... Chapter 3 touches on memory addressing modes. The 601 was more compatible with the full POWER ISA that came before it, but looking at the docs for the POWER ISA itself would probably be more instructive.