4 ms·

If they were 8-bit, shouldn't they have supported 2 digits at at time (4 bits per digit)?

by bjackman 11y ago

Animats 11y ago
6 bits of data, one bit of mark, and 1 bit of parity only visible to the parity checking hardware.
- mikepavone 11y ago
  That's not the format used by the x86 BCD instructions. x86 (and the 8080 before it) use 4-bit packed BCD so each byte contains two digits (x86 also has instructions for dealing with unpacked BCD, but the digits are still 4-bit). Additionally, the 8086 was a 16-bit processor (the 8088 had an 8-bit bus, but that came later and was still 16-bit internally) so I don't think the 8-bit limitation is due to the word size of the CPU in this case. It could be a holdover from the 8080 (8086 isn't binary compatible, but it was marketed as "source" compatible so there's a fair amount of similarity), but the 68000 (16-bit implementation of a 32-bit ISA) has the same limitation. I think it probably comes down to cost. Just to support two packed digits, you need a fair bit of extra hardware (or a little extra hardware and a bunch of microcode) so you can properly calculate the correction factor. Expanding this to a full word means you need to be able to do that calculation for 4 nibbles instead of 2 which is about 3 times worse (you effectively get the most significant nibble "for free" so it's 3 extra nibbles to support instead of just 1).
kens 11y ago
Let me try to fix the confusion in this subthread. The 8080, Z-80, 6502, etc are 8-bit processors that support BCD arithmetic, 2 digits at a time. The 6502 has a decimal mode flag that enables BCD arithmetic. The 8080 and descendants use a DAA (Decimal Adjust Accumulator) instruction that fixes up the BCD digits after doing a binary add. The x86 supports packed BCD (2 digits per byte) or unpacked BCD (1 digit per byte) in the general purpose registers, and 10-byte, signed 18 digit BCD integers in the FPU registers. It has additional adjust operations DAS (Decimal Adjust after Addition), AAA, AAS, AAM, AAD (ASCII Adjust after Addition/Subtraction/Multiplication/Division for unpacked values). The 1401 is a decimal machine with one BCD digit per character. It has 6-bit characters, along with a word mark bit and a parity bit with each character.

If they were 8-bit, shouldn't they have supported 2 digits at at time (4 bits per digit)?

Animats 11y ago

6 bits of data, one bit of mark, and 1 bit of parity only visible to the parity checking hardware.

mikepavone 11y ago
That's not the format used by the x86 BCD instructions. x86 (and the 8080 before it) use 4-bit packed BCD so each byte contains two digits (x86 also has instructions for dealing with unpacked BCD, but the digits are still 4-bit). Additionally, the 8086 was a 16-bit processor (the 8088 had an 8-bit bus, but that came later and was still 16-bit internally) so I don't think the 8-bit limitation is due to the word size of the CPU in this case. It could be a holdover from the 8080 (8086 isn't binary compatible, but it was marketed as "source" compatible so there's a fair amount of similarity), but the 68000 (16-bit implementation of a 32-bit ISA) has the same limitation. I think it probably comes down to cost. Just to support two packed digits, you need a fair bit of extra hardware (or a little extra hardware and a bunch of microcode) so you can properly calculate the correction factor. Expanding this to a full word means you need to be able to do that calculation for 4 nibbles instead of 2 which is about 3 times worse (you effectively get the most significant nibble "for free" so it's 3 extra nibbles to support instead of just 1).

kens 11y ago

Let me try to fix the confusion in this subthread. The 8080, Z-80, 6502, etc are 8-bit processors that support BCD arithmetic, 2 digits at a time. The 6502 has a decimal mode flag that enables BCD arithmetic. The 8080 and descendants use a DAA (Decimal Adjust Accumulator) instruction that fixes up the BCD digits after doing a binary add. The x86 supports packed BCD (2 digits per byte) or unpacked BCD (1 digit per byte) in the general purpose registers, and 10-byte, signed 18 digit BCD integers in the FPU registers. It has additional adjust operations DAS (Decimal Adjust after Addition), AAA, AAS, AAM, AAD (ASCII Adjust after Addition/Subtraction/Multiplication/Division for unpacked values). The 1401 is a decimal machine with one BCD digit per character. It has 6-bit characters, along with a word mark bit and a parity bit with each character.